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AR# 20008

6.3 System Generator for DSP - Release Notes and Known Issues List

Description

General Description:

What are the known issues for System Generator v6.3?

Solution

6.3 System Generator for DSP - Release Notes and Known Issues List

Support Software Issues

1. What software do I need to install System Generator for DSP? Please see (Xilinx Answer 17966).

2. XST bus elaboration might cause interface changes. Please see (Xilinx Answer 18650).

3. QAM16 demo fails to compile when using Leonardo Spectrum. Please see (Xilinx Answer 19503).

Xilinx Block Set Issues

1. The CIC filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. To work around this problem, do not use the full dynamic range of your input. Please see (Xilinx Answer 12480).

2. PicoBlaze fails to compile when using the Leonardo synthesis tool. Please see (Xilinx Answer 16923).

3. PicoBlaze compiler script fails when using long module names. Please see (Xilinx Answer 16924).

4. There are simulation mismatches for the FFTx when the VOUT is Low. Please see (Xilinx Answer 18645).

6. Missing clock/clock enable pair when importing HDL as a black box. Please see (Xilinx Answer 19500).

7. Missing clock/clock enable pair when importing VHDL as a black box. Please see (Xilinx Answer 20198).

8. Simulation mismatched for the reloadable DA FIR, when doing back annotated simulation. Please see (Xilinx Answer 19505).

9. Verilog simulation mismatch when using the Dual Port BlockRAM. Please see (Xilinx Answer 20200).

10. Reset must be asserted when using the embedded option for the FIFO Block. Please see (Xilinx Answer 20201).

11. VHDL simulation mismatches when using the embedded option for the FIFO Block. Please see (Xilinx Answer 20203).

12. Verilog simulation mismatched when using the FIFO Block. Please see (Xilinx Answer 20205).

13. Verilog generation when using the embedded option for the FIFO Block. Please see (Xilinx Answer 20206).

14. Xilinx Communications Reference block set does not open on Japanese OS. Please see (Xilinx Answer 20207).

15. AWGN reference block uses too many Block RAMs. Please see (Xilinx Answer 20208).

16. Resource Estimator causes error when not currently selected block. Please see (Xilinx Answer 20211).

17. Multiplier block simulation and hardware latency mismatch. Please see (Xilinx Answer 20213).

General Issues

1. The following error is reported during generation: "Undefined function or variable." Please see (Xilinx Answer 15190).

2. Documentation for older versions of System Generator for DSP are not available after install. Please see (Xilinx Answer 18642).

3. Generation fails when the Simulation Stop Function is defined for a model. Please see (Xilinx Answer 18623).

4. User Hardware Co-Sim files disappear when installing System Generator for DSP update. Please see (Xilinx Answer 18646).

5. There is no system-level reset signal available for System Generator for DSP designs. Please see (Xilinx Answer 19498).

6. JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. Please see (Xilinx Answer 19599).

7. Verilog block support error when trying to generate a VHDL netlist. Please see (Xilinx Answer 20120).

8. HDL Co-Simulation resolution mismatches. Please see (Xilinx Answer 20209).

9. Some of the DSP48 examples will not generate. Please see (Xilinx Answer 20212).

10. Incremental netlist project error when opened in Project Navigator. Please see (Xilinx Answer 20420).

AR# 20008
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article