AR #20017 - LogiCORE SPI-4.2 (POS-PHY L4) - Which I/O Standards (IOSTANDARD) are supported for the SPI-4.2 Core?

AR#	20017
Part	SW-Coregen
Last Modified	2009-06-20 00:00:00.0
Status	Active
Keywords	CORE Generator, IP, update, PL4, packet, sonnet, physical, link, layer, source, synchronous, phase, alignment, IO banking, rules, digital, controlled, impedence, impedance, DCI

Solution

To define the appropriate I/O standards, you must add them in the User Constraint File (UCF).

The following is an example of the correct format to use for the UCF:

NET "RDat_P(0)" IOSTANDARD = LVDS_25_DCI;

This example defines the RDat_P(0) bit to have an I/O with LVDS 2.5 volts with internal device termination.

Other supported standards are listed below. Each group of signals has different supported standards for each specific device family. Note that Virtex-6 does not support LVTTL.

SysClk
Virtex-II: LVPECL_33, LVDS_25
Virtex-II Pro: LVPECL_25, LVDS_25, LVDS_25_DCI
Virtex-4, Virtex-5: LVPECL_25, LVDS_25, LVDS_25_DCI
Virtex-6: LVDS_25, LVDS_25_DCI, LVPECL_25

RStat, RSClk
Virtex-II: LVTTL, LVDS_25
Virtex-II Pro: LVTTL, LVDS_25
Virtex-4, Virtex-5: LVTTL, LVDS_25
Virtex-6: LVDS_25, LVDS_25_DCI

TStat, TSClk
Virtex-II: LVTTL, LVDS_25, LVDS_25_DCI
Virtex-II Pro: LVTTL, LVDS_25, LVDS_25_DCI
Virtex-4, Virtex-5: LVTTL, LVDS_25, LVDS_25_DCI
Virtex-6: LVDS_25, LVDS_25_DCI

TDat, TDClk, TCtl
Virtex-II: LVDS_25
Virtex-II Pro: LVDS_25, LVDS_25_DCI
Virtex-4, Virtex-5: LVDS_25, LVDS_25_DCI
Virtex-6: LVDS_25, LVDS_25_DCI

RDat, RDClk, RCtl
Virtex-II: LVDS_25
Virtex-II Pro: LVDS_25, LVDS_25_DCI
Virtex-4, Virtex-5: LVDS_25, LVDS_25_DCI
Virtex-6: LVDS_25, LVDS_25_DCI


Revision History
04/13/2009 - Initial Release
06/24/2009 - Updated with Virtex-6 information