When I simulate with the VHDL demonstration testbench, a "value out of range" error occurs.
This problem is fixed in SPI4.2 v7.1 released with IP Update #4.
This problem is caused by an out-of-range condition on the TDatSinceTrain variable in "pl4_data_monitor.vhd" and can be triggered by the following two conditions:
- Periodic training is never sent by the Source core (when Number of Data Cycles before Training = 0 or Number of Training Patterns during Training = 0).
- Periodic training is sent more than 65535 clock cycles apart (when Number of Data Cycles before Training + (Burst Size in Credits * 8) > 65535).
Change the Source Core options using Option A or Option B:
- Change the options so that the Source Core sends training periodically
- Number of Data Cycles before Training is set to less than 65535 (Burst Size in Credits * 8)
- Burst Mode is set to "Complete Burst Only"
- Number of Data Cycles before Training is set to less than 65527
- Burst Mode is set to "Segmentation of Burst at Credit Boundary"
Edit the VHDL demonstration testbench to prevent TDatSinceTrain from overflowing. In "pl4_data_monitor.vhd", change the following line (in two places).
Change this line:
TDatSinceTrain <= TDatSinceTrain + 1 after TFF;
TDatSinceTrain <= (TDatSinceTrain + 1) mod 65536 after TFF;
NOTE: Regenerating the SPI-4.2 Core from the CORE Generator overwrites "pl4_data_monitor.vhd"; consequently, any changes made by you are lost.