UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20031

LogiCORE SPI-4.2 (POS-PHY L4) v7.0 - Simulation: "Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;"

Description

General Description

When I perform a timing simulation (post-PAR simulation with SDF) of an SPI-4.2 core, numerous hold violation warnings similar to the following occur:

"# ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;

# Expected := 0.316 ns; Observed := 0.178 ns; At : 17494.406 ns

# Time: 17494406 ps Iteration: 3 Instance:

/pl4_tstbench/pl4_top_lb0/pl4_test_timing29402_12_pl4_snk_top0_u0_core0_queue0_frdadrx_reg_gray_addr3"

"# ** Error: /proj/xbuilds/GmmS1.2/verilog/src/simprims/X_FF.v(40): $hold( posedge CLK:27873227 ps, negedge I &&& (in_clk_enable == 1):27873227 ps, 316 ps );

# Time: 27873227 ps Iteration: 0 Instance: /pl4_tstbench/pl4_top_lb0/\pl4_test_timing29402_12_pl4_src_top_master_addr0/U0/core0/fifo0/PL4_Source_FIFO/reg_addr_xfr_gray/reg_gray_addr0"

Solution

Hold violations and errors on signals internal to the core with names ending in "output_ff" or "reg_gray_addr[*]" are a result of signals crossing clock boundaries and can be safely ignored.

AR# 20031
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article