Solution

Issues Addressed in 8.2i Service Packs



CompXLib



(SP3) - (Xilinx Answer 23977) - 8.2i CompXLib - VHDL models are not getting compiled in ISE 8.2i SP1 with VCS_MX



Constraints & Timing



(SP3) - (Xilinx Answer 23936) - 8.2i TRACE/Timing Analyzer - Why is the clock skew always reported as zero?

(SP3) - (Xilinx Answer 23937) - 8.2i TRACE/Timing Analyzer - Missing intermediate signals in detailed path report when crossprobing

(SP2) - (Xilinx Answer 23747) - 8.2i Virtex-5, Timing Analyzer - Why are Q1's and Q2's paths analyzed on both edges?

(SP2) - (Xilinx Answer 23431) - 8.2i Virtex-5, Create Timing Constraint Process - "ERROR:ConstraintsEditorC - Please enter a number..." message

(SP2) - (Xilinx Answer 23778) - 8.2i Constraints Editor - Crashes on Global tab/category on PERIOD cell of 1 ms

(SP2) - (Xilinx Answer 23782) - 8.2i Virtex-5 - Constraints Editor - Distributed RAMs not listed in the Create Group by Instance constraints

(SP2) - (Xilinx Answer 23421) - 8.2i Virtex-5, Constraints - Unable to lock (LOC) placement of global logic components (RAM, PPC, DCM, etc.)

(SP2) - (Xilinx Answer 23429) - 8.2i Virtex-5, Constraints - Unable to place (LOC) I/O via distribution button or to I/O Banks, and no tool tips during drag and drop

(SP1) - (Xilinx Answer 23422) - 8.2i Virtex-5, Constraints - Unable to create Area Constraints on Clock Regions, for timegroups, or the top level

(SP1) - (Xilinx Answer 23629) - 8.2i Virtex-5, Constraints - Slice-based area_group disappears if I resize / move it to invalid location

(SP1) - (Xilinx Answer 23632) - 8.2i Virtex-5, Constraints - Pin assignment made to specific locations cannot be made



CPLD



(SP2) - (Xilinx Answer 23534) - 8.1i NGDBuild CPLDFit: FDCPE - Clock Enable logic is incorrectly removed



Data2BRAM



(SP3) - (Xilinx Answer 23979) - 8.2i Data2Mem - Multi-processor designs fail when using shared block RAM memories

(SP3) - (Xilinx Answer 23980) - 8.2i Data2Mem - Data2Mem does not support the initialization of 36K block RAM memory spaces in the 5VLX50T Device



Floorplan Editor



(SP2) - (Xilinx Answer 23781) - 8.2i Virtex-5, Floorplan Editor - Connections from Pad to buffer are not displayed

(SP2) - (Xilinx Answer 23798) - 8.2i Floorplan Editor - Partition ranges are not retained in the Design Object List

(SP2) - (Xilinx Answer 23802) - 8.2i Floorplan Editor - Cannot allow a site after prohibiting it

(SP2) - (Xilinx Answer 23786) - 8.2i Floorplan Editor - "Fatal Error: GuiUtilities" error occurs when cross-probing between Timing Analyzer and Floorplan-Implemented view

(SP1) - (Xilinx Answer 23423) - 8.2i Virtex-5, Cross-Probing - The complete path is not shown in Floorplan-Implemented tab



iMPACT



(SP2) - (Xilinx Answer 23734) - 8.2i iMPACT - Deleting the last revision does not update the PROM Capacity

(SP2) - (Xilinx Answer 23737) - 8.2i iMPACT - When selecting an SPI PROM, the files are generated for the wrong size of PROM

(SP2) - (Xilinx Answer 23742) - 8.2i iMPACT - "ERROR:iMPACT:2874 - Failed to copy file..." after Save Archive File for the xc9500xl

(SP2) - (Xilinx Answer 23743) - 8.2i iMPACT - iMPACT crashes in Linux when the ".bit" file targeted for a device has been updated

(SP2) - (Xilinx Answer 23745) - 8.2i iMPACT - V-5 multiboot wizard should not allow user to add non V-5 device at the start of the chain

(SP2) - (Xilinx Answer 23746) - 8.2i iMPACT - Error: 1353 ACD entry READ_INSTRUCTION not found for device family AT45DBxxxx



MAP



(SP3) - (Xilinx Answer 23972) - 8.2i SP3 Virtex-5 MAP - Enhancement to retarget Virtex-4 RAMB16s to Virtex-5 RAMB18SDPs

(SP3) - (Xilinx Answer 23973) - 8.2i Virtex-5 MAP - Write address line of RAM128X1D incorrectly optimized when SPO is unused

(SP3) - (Xilinx Answer 23974) - 8.2i Virtex-4 MAP - Design with DSPs crashes after message "mapping design into LUTs"



PACE



(SP2) - (Xilinx Answer 23779) - 8.2i PACE - IOBDELAY Constraints removed from UCF



PAR



(SP3) - (Xilinx Answer 23978) - 8.2i Virtex-4 PAR - Placer hangs in Phase 5.30

(SP3) - (Xilinx Answer 23981) - 8.2i Virtex-4 PAR - Crash in Phase 8.8

(SP3) - (Xilinx Answer 23982) - 8.2i PAR - MPPR fails during 2nd cost table



Project Navigator



(SP2) - (Xilinx Answer 23427) - 8.2i Virtex-5, Project Navigator - Crashes when sorting columns, cross-probing, or placing components

(SP2) - (Xilinx Answer 23799) - 8.2i ISE - Generate Formality Netlist for a Virtex-5 project gives: "ERROR:NetListWriters:437 - Unknown output netlist type"

(SP2) - (Xilinx Answer 23793) - 8.2i ISE - Removing "Simulation Only" file in Project Navigator changes the Implementation status to "Out of Date"

(SP2) - (Xilinx Answer 23794) - 8.2i ISE - Using Virtex-5 and Reentrant Route mode fails with "ERROR: <top_module>.ncd does not exist"

(SP2) - (Xilinx Answer 23341) - 8.2i ISE - Creating new Project Navigator project fails with message: "The project location <directory path> is read only. Please try another location."

(SP2) - (Xilinx Answer 23458) - 8.2i ISE - Project Navigator process status and partition information is lost when snapshot is made current

(SP2) - (Xilinx Answer 23795) - 8.2i ISE - Project Navigator "Clean All Project Files" deletes ".mif" files added to the project

(SP2) - (Xilinx Answer 23796) - 8.2i ISE - Synthesis and Implementation processes are not available for an HDL source, even when the source is set as top level

(SP2) - (Xilinx Answer 23797) - 8.2i ISE - Using package files incorrectly triggers "WARNING:ProjectMgmt - Problems were detected in the project file during open"

(SP2) - (Xilinx Answer 23383) - 8.2i ISE - Project Navigator runs a process on a source unrelated to the selected top-level module

(SP2) - (Xilinx Answer 23530) - 8.2i ISE - Project Navigator reruns Xplorer script unnecessarily after re-opening a project

(SP2) - (Xilinx Answer 23800) - 8.2i ISE - Project Navigator Assign Package Pins process does not get the "Part" specification in a CPLD/EDIF project

(SP1) - (Xilinx Answer 23555) - 8.2i ISE - Collapsed source view of User Documents added to a Project Navigator project keeps getting expanded

(SP1) - (Xilinx Answer 23554) - 8.2i ISE - Project Navigator "Assign Package Pins" process does nothing with NGC Project

(SP1) - (Xilinx Answer 23381) - 8.2i ISE - Creating a new EDIF-based project with New Project Wizard causes fatal error from GuiUtilities:Gq_Application.c when UCF file is included

(SP1) - (Xilinx Answer 23458) - 8.2i ISE - Project Navigator process status and partition information is lost when Snapshot is made current

(SP1) - (Xilinx Answer 23102) - 8.2i ISE - Project Navigator hangs when opening specific projects -- project file becomes corrupt

(SP1) - (Xilinx Answer 23553) - 8.2i ISE - Project Navigator shows intermediate files generated by ISE processes in Sources window

(SP1) - (Xilinx Answer 23262) - 8.2i ISE - Project Navigator shows that MAP failed, but there are no errors in my MAP report

(SP1) - (Xilinx Answer 23387) - 8.2i ISE - Project Navigator crashes when closing one project and trying to open another -- GuiUtilities:Gq_Application.c:570:1.12.10.2

(SP1) - (Xilinx Answer 23551) - 8.2i ISE - Apply Project Properties process closes project and hangs Project Navigator

(SP1) - (Xilinx Answer 22570) - 8.1i ISE - When I launch ModelSim with a custom ".do" file, the following message appears: "# invalid command name"

(SP1) - (Xilinx Answer 23385) - 8.2i ISE - Project Navigator lists inaccurate options for Virtex-5 Configuration Rate

(SP1) - (Xilinx Answer 23550) - 8.2i ISE - Running the MPPR option "Copy result to Working Directory" causes project processes to go out-of-date

(SP1) - (Xilinx Answer 23549) - 8.2i ISE - "Back Annotate Pin Locations" process does not use correct UCF file if the base name does not match the Top Level source name



Speeds Files



(SP2) - (Xilinx Answer 23788) - Virtex-5 - Speeds File Revision History

(SP2) - (Xilinx Answer 20953) - Virtex-4 - Speeds File Revision History

(SP2) - (Xilinx Answer 21299) - Spartan-3E - Speed File Revision History



Simulation



(SP2) - (Xilinx Answer 23735) - 8.2i Virtex-5 - FIFO36_72 ALMOST_FULL / ALMOST_EMPTY parameters improperly defined as 9 bits wide

(SP1) - (Xilinx Answer 23461) - 8.1i ISE - The hourglass mouse pointer does not change after using the Test Bench Waveform (TBW) wizard

(SP1) - (Xilinx Answer 23641) - 8.1sp1 UniSim, Simulation - FIFO16 UniSim model Xs out ALMOST_EMPTY flag and DO output

(SP1) - (Xilinx Answer 23647) - 8.1.03i UniSim, Simulation - DLL does not lock during Verilog simulation and does not generate any output clock



TCL



(SP1) - (Xilinx Answer 23441) - 8.2i TCL - No Error code appears when implementation fails in TCL script

(SP1) - (Xilinx Answer 23437) - 8.2i TCL - "Project set family Virtex4" command causes ERROR:TclTaskC



UniSim



(SP3) - (Xilinx Answer 23983) - 8.2i UniSim, Simulation - PLL output ( CLKOUT0) is 180 degrees out of phase with clock input ( CLKIN1)



XST



(SP3) - (Xilinx Answer 23984) - 8.2i XST - "ERROR:Xst:2587 - Port %s of instance %s has different type in definition %s"

(SP3) - (Xilinx Answer 23976) - 8.2i NetGen - NetGen generates an SDF file that does not have Delay/Timing check information for X_PLL_ADV

(SP3) - (Xilinx Answer 23975) - 8.2i ISE - PLL_ADV VHDL model does not phase shift when CLKFBOUT_MULT and CLKOUTx_DIVIDE attributes are set to 1

(SP1) - (Xilinx Answer 23648) - 8.1i XST - Incorrect logic is generated by XST when trying to infer an open drain driver for CPLD

(SP1) - (Xilinx Answer 23446) - 8.1i/7.1 XST- "ERROR:Xst:71 - Redeclaration of an instance : <instance_name>"

(SP1) - (Xilinx Answer 23334) - 8.1i XST - XST generates incorrect logic when an integer type is used in a record type in VHDL