Is the Virtex-4 System Monitor feature supported?
The Virtex-4 System Monitor feature is NOT supported. System Monitor and ADC components were removed from Xilinx ISE design tools starting with version 6.3i.
Please refer to Virtex-4 errata for more information at:
Although System Monitor is not supported, there are connection requirements for its dedicated pins that should be followed. For additional information, refer to the Virtex-4 Packaging and Pinout Specification at:
Xilinx requires tying AVDD_SM to 2.5 V (Vccaux is acceptable); VREFP_SM, VREFN_SM, VP_SM, VN_SM, and AVSS_SM should all be grounded.
Can the user deviate from the recommendations?
While any connections other than those recommended have not been fully tested, the following guidelines apply:
- The GND reference pins (AVSS_SM and VREFN) must NOT be tied to any Vcc supply and must be tied to GND. Failure to met this requirement will damage the FPGA. Xilinx cannot support any designs that do not have AVSS_SM and VREFN connected to GND.
- If AVDD_SM were connected to GND accidentally, this will not cause any damage to the Virtex-4 device.
- The analog inputs VP and VN have ESD protection that is tied off to AVDD_SM and AVSS_SM. If AVDD_SM is connected to 2.5V, then VP and VN can be connect to 2.5V or GND. If all supplies are grounded, then VP and VN should be connected to GND, as indicated in the User Guide. Due to untested and potential latchup/ESD issues, no pin should be left floating.