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AR# 20156

6.3 ISE / EDK - Error in ISE instantiation template created for an XMP source - Redeclaration of symbol system

Description

Keywords: EDK, XMP, ISE, Source, VHDL, Instantiation Template

Urgency: Standard

General Description:
In an ISE project with an XMP (Xilinx Microprocessor Project) file as source, the "View HDL Instantiation Template'' generated has the identical component and instance names. Here is an example of the generated code:

begin

system : system
port map (
fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin_IBUF,
fpga_0_RS232_TX_pin => fpga_0_RS232_TX_pin_OBUF,

This is incorrect VHDL because the instance name cannot be the same as the design name; hence, I receive an error when I run XST:

"Compiling vhdl file S:/xps/edkgmm8_g352_xp2/top.vhd in Library work.
ERROR:HDLParsers:1202 - S:/xps/edkgmm8_g352_xp2/top.vhd Line 117. Redeclaration of symbol system."

To see the error, select "top.vhd" and run 'Synthesize'.

Solution

To work around this issue, save the HDL Instantiation Template to a new name and modify the instance name. Here is an example of the instantiation:

begin

u1 : system
port map (
fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin_IBUF,
fpga_0_RS232_TX_pin => fpga_0_RS232_TX_pin_OBUF,

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 3.
AR# 20156
Date Created 10/12/2004
Last Updated 03/20/2006
Status Archive
Type General Article