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AR# 20203

6.3 System Generator for DSP - Why do I see a mismatch between the System Generator simulation and the VHDL behavioral simulation when using the FIFO Block with type "Embedded FIFO" (FIFO16)?

Description

General Description: 

Why do I see a mismatch between the System Generator simulation and the VHDL behavioral simulation when using the FIFO Block with type "Embedded FIFO" (FIFO16)?

Solution

This is a known issue with the FIFO16 VHDL UniSim model. The UniSim almost empty and almost full offset settings offset the correct setting by one clock, causing mismatches in both behavioral and post-translate simulations. This has been fixed in ISE 6.3, Service Pack 1.

AR# 20203
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article