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AR# 20205

8.1 System Generator for DSP - Why do I see a mismatch between the System Generator simulation and the Verilog behavioral simulation when using the Distributed or BlockRAM FIFO?

Description

Why do I see a mismatch between the System Generator simulation and the Verilog behavioral simulation when using the Distributed or BlockRAM FIFO?

Solution

It is currently known that the Verilog behavioral model for the Synchronous FIFO 5.0 Core does not match the System Generator for the DSP model. This problem occurs when you select Distributed or BlockRAM, but not when using the Embedded option. 

 

To work around this problem, you should perform a post translate simulation. 

 

This issue is fixed in System Generator for DSP 8.1.01, scheduled for release in April 2006.

AR# 20205
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article