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AR# 20213

6.3 System Generator for DSP - Why do I see a difference between the Multiplier Block simulation latency and hardware latency when targeting Virtex-4?

Description

General Description: 

Why do I see a difference between the Multiplier Block simulation latency and hardware latency when targeting Virtex-4?

Solution

This is a known issue. The post Translate, post MAP, and post PAR simulations, as well as the hardware implementation, are 1 clock cycle of latency behind the behavioral and Simulink simulation. 

 

For more information, please see (Xilinx Answer 20777).

AR# 20213
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article