We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20214

LogiCORE FIFO Generator v1.1 - Virtex-4 with "FIFO16 implementation" might corrupt data


General Description: 

When using FIFO Generator core v1.1, with FIFO16 implementation, you might see data corruption in the FIFO core. This is applicable only to Virtex-4 designs, and the data corruption might be seen in gate-level simulation (post-NDGBuild, post-MAP, and timing) and in the device.


All customers targeting Virtex-4 devices, using FIFO Generator core with "FIFO16 Implementation" should use FIFO Generator v2.0 core, which will be available with IP Update #4 release, scheduled for mid November 2004.

AR# 20214
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article