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AR# 20219

LogiCORE FIFO Generator v2.0 - Release Note and Known Issues

Description

Keywords: CORE, Generator, COREGen, IP, update, #4, ip4_g, gip_4, asynchronous, asynch, synchronous, fifo16, block RAM, asymmetric, ports, programmable, assert, negate

Urgency: Standard

General Description:
This Release Note is for the FIFO Generator v2.0 released in 6.3i IP Update #4. It contains:

- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 20083).

This new version of the FIFO Generator COREGen Core includes enhanced support for the FIFO16 primitive in the Virtex-4 architecture. If you intend to target Virtex-4, you must upgrade to this latest FIFO Generator Core which includes enhancements and bug fixes critical to Virtex-4 and 6.3i SP2 Tools. To generate a FIFO16-based FIFO from the FIFO Generator GUI:

1. Open Core Generator GUI.
2. Select Virtex-4 as the Target Architecture under Project -> Project Options.
3. Open the FIFO Generator V2.0 GUI.
4. Select "Independent Clocks" under "Read Write Clock Domains."
5. Select "FIFO 16-primitive based FIFO" under FIFO Implementation (click the pull-down selection).
6. Memory Type "FIFO16" will automatically be selected.

Solution

New Features in v2.0
- Programmable Thresholds for FIFO16 implementation.
- Significantly faster Verilog behavioral model.
- ASYNC_REG attribute added to registers with clock-crossing domains

Bug Fixes in v2.0
- CR 196806: Netlist issue
Symptom: Data corruption and metastability issues due to the synchronization of FIFO16 with the internal read and write clocks. See the FIFO Generator data sheet and (Xilinx Answer 20214) for more details.

- CR 197001: Netlist issue
Symptom: "X" value propagating through to handshaking and programmable signals if Reset flip-flop fails to meet setup and hold time.

- CR 179309: Verilog Behavioral Simulation issue
Symptom: The EMPTY, ALMOST_EMPTY should be switching only on RD_CLK, and FULL and ALMOST_FULL flags should only be switching on WR_CLK, but both sets of signals are switching on both clocks. Fixed Verilog behavioral model.

- CR 190997: Simulation issue
Symptom: When running the FIFO with synchronous clocks and registering the RD_EN signal on the rising edge of the RD_CLK, the EMPTY flag might toggle instantaneously in response to a change in the RD_EN input in functional simulation instead of modeling the delay that would be seen following assertion of RD_EN in the implemented core.

- CR 192595: Simulation issue
Symptom: The core does not assert the EMPTY signal at startup unless the RESET signal has been asserted.

- CR 192810: GUI issue
Symptom: Message referring user to the data sheet has been removed because of the complexity of the equations for the write and read depth of the asynchronous implementation. Basically, the depths are designed to make it possible to differentiate between the FULL and EMPTY states for the asynchronous FIFO. The read and write depths equations are different for all 4 different FIFO implementations. The equations depend on type of primitives (i.e., FIFO16), number of cascaded primitives, and read and write pointer designs.

- CR 187671: GUI issue
Symptom: DOUT Reset should be available when target family is set to Virtex-4.

- CR 188346: XST issue
Symptom: DOUT Reset Value is wrong when the read depth is multiples of two of the write depth.

- CR 191537: Netlist issue
Symptom: FULL will not go Low after reading one word from the FIFO if WR_EN is still asserted and FIFO is FULL.

Known Issues

- GUI allows user to choose illegal output depths (depths < 16) for asymmetrical asynchronous implementation of the FIFO.
Please see (Xilinx Answer 20272). (CR197000)

- Incorrect range for Programmable Empty Assert and Negate threshold. When using a FIFO16-based FIFO Generator and when the "Output Depth" specified by the user on page 1 is equal to, or less than, the "Fifo16 Primitive Depth" selected, the ranges provided on page 2 will be incorrect.
Please see (Xilinx Answer 20273). (CR197358)

- In a FIFO16-based FIFO Generator implementation, when the output depth is larger than the selected Input Depth, it is possible for PROG_EMPTY and PROG_FULL to produce false-assert values if the Programmable Empty or Programmable Full thresholds are near the limits of their range.
Please see (Xilinx Answer 20278). (CR197535)

- When using an Asynchronous clock with Block Memory type, you might see an error during back-annotated simulaton (gate-level and timing) at the reset. Please see (Xilinx Answer 20271). (CR197268)

- During simulation, you might receive set up and hold time violations.
Please see (Xilinx Answer 20291). (CR197002)

- For synchronous clock FIFO implementation, the Verilog behavioral model simulation of PROG_EMPTY flag near the user-specified threshold differs slightly from the VHDL simulation. This only happens at the user-specified threshold. In the Verilog simulation, PROG_EMPTY flag may not be asserted or de-asserted at right the threshold. However, above or below the threshold, the PROG_EMPTY will be in the correct state. If you do not expect the PROG_EMPTY flag to be asserted or de-asserted instantly at the threshold, but rather a cycle or two later, this will not be an issue. (CR197255)
AR# 20219
Date Created 09/03/2007
Last Updated 10/04/2005
Status Active
Type General Article