I want to modify my PowerPC memory-system features. I want to configure the Core-Configuration Register (CCR0) for my system.
What should I be aware of when making modifications, and what is the reset value of the CCR0? There is a discrepancy in the PowerPC Processor Reference Guide in the "SPR Contents Following Reset" table in the Reset and Initialization chapter, which states that the CCR0 is assigned to 0x00700000 at reset. However, the "Special-Purpose Registers Sorted by Name," "Special-Purpose Registers Sorted by SPRN," and "Special-Purpose Registers Sorted by SPRF" tables in the Register Summary appendix state that its reset value is undefined. Which value is correct?
Xilinx recommends using 0x50700000 as the reset value for the CCR0 register. Starting with EDK 8.1i, the boot code has set the reset value for the CCR0 register as 0x50700000 (this applies only to Virtex-4).
The above reset value sets up the CCR0 as follows:
BITNumber Name Function
Bits 0:5 Reserved
Bit 6 LWL Load Word as Line set to 0-Load only requested data
Bit 7 LWOA Load Without Allocate set to 0-Allocate
Bit 8 SWOA Store Without Allocate set to 0-Allocate
Bit 9 DPP1 DCU PLB-Priority Bit 1 set to 1-DCU PLB priority 1 on bit 1
Bits 10:11 IPP ICU PLB-Priority Bits 0:1 set to 03-Highest PLB req priority
Bits 12:13 Reserved
Bit 14 U0XE Enable U0 Exception set to 0-Disabled
Bit 15 LDBE Load-Debug Enable set to 0-Load data is not visible on the data-side OCM
Bits 16:19 Reserved
Bit 20 PFC Prefetching for Cacheable Regions set to 0-Disabled
Bit 21 PFNC Prefetching for Noncacheable Regions set to 0-Disabled
Bit 22 NCRS Non-Cacheable Request Size set to 0-Request size is four words
Bit 23 FWOA Fetch Without Allocate set to 0-Allocate
Bits 24:26 Reserved
Bit 27 CIS Cache-Information Select set to 0-Information is cache data
Bits 28:30 Reserved
Bit 31 CWS Cache-Way Select set to 0-Cache way is A
For more information, see the PowerPC Processor Reference Guide at:
Go to the "Core-Configuration (CCR0) Register Field Definitions" table in Memory-System Management -> Cache Control -> Core-Configuration Register.
Xilinx has not found any performance improvements with modifications to this register and recommends using the reset value for all systems. If your system is going to perform cacheline transactions for descriptors and data, include the descriptors and the data areas in cacheable memory, then flush the regions after writing or before reading.
For usage information on how to flush the cache, refer to the XCache_Flush function, in your EDK install located at:
The work-around only needs to be applied to silicon in which the PVR (processor version register) of the PPC405 has a value of 0x20011430. Silicon in which the PPC405 has a PVR of 0x20011470 does not need the work-around (i.e., CCR0 can be left at the original reset value). All production silicon has PPC405s with PVR 0x20011470.
Based on this information, the boot code can be modified to change the CCR0 reset value to 0x50700000.