Can the RDY/BSY signal be used to indicate when asynchronous peripheral mode
configuration can commence instead of using the INIT pin?
The RDY/BSY pin may be used to indicate when the FPGA can accept configuration
data in asynchronous peripheral mode. However, a pulldown
should be used to keep this pin at a logic low during power-up.
After Vcc has been applied to the FPGA, but before the mode pins have been
sampled, all I/Os, including the RDY/BSY pin, will be high-impedence and
pulled high. After the mode pins have been sampled, if APM has been
selected, then the RDY/BSY pin will be driven low during a memory clearing
cycle. When the FPGA is ready to accept configuration data the RDY/BSY pin
will be driven HIGH. Adding a 2.2~3.3K ohm resistor to this pin will hold it
LOW until the FPGA can accept data.