When I use Asynchronous clocks with Block Memory type, an error similar to the following occurs during back-annotated simulation (gate-level and timing):
"Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(
posedge CLKA:815843114 ps, posedge SSRA &&& ENA:815843180 ps, 280 ps );
# Time: 815843180 ps Iteration: 0 Instance:
This error is produced on the rising edge of the user reset input. The reason for this is that the Block Memory only has a synchronous reset input, while the FIFO Generator Core has an asynchronous reset. While the FIFO Generator reset is synchronized to the clock, it is only synchronized to insure that the reset pulse is of adequate width to properly reset the core, and that the release of the reset is properly timed relative to the clock. Therefore, the rising edge of the user reset still reaches the synchronous reset input to the block RAM asynchronously, and this causes a timing violation.
Once the block RAM is clocked, the reset occurs as it should. This should cause no problems with the behavior of the core, since once the synchronous reset event occurs on the block RAM, all signals should go to their proper state.