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AR# 20287

XC9500/XL/XV CPLD - Can I program XC9500 CPLDs with an SVF file?


Can I program XC9500 (XL/XV) CPLDs with an SVF file?


Xilinx does not recommend programming XC9500 (XL/XV) devices with an SVF. The programming algorithms for these devices can repeat steps if programming does not succeed. SVF files do not include this looping functionality. However, XSVF files do have this functionality and are recommended.

The SVF files are created with a 10 ms wait time after each page is programmed into the device. Typical looping functions will only need to loop the wait time in the SVF file 3 times for successful completion. This same effect can be applied to the entire file by multiplying the runtest of 10000 by 3.

The hardware in the 9500 devices supports a max programming time of 80 ms. If the SVF file wait times are to be expanded the upper bounded limit is 80 ms. Waiting beyond 80 ms will move the device out of the programming state and into an idle state. If the programming time is not a factor, the runtest 10000 statements in the svf file can be expanded by a factor of 8.

The root cause of the issue is due to the fabric of the 9500 (XL/XV) devices. These devices have a basic internal programming engine which will not loop the programming cycle itself, and this operation is typically done by the programming algorithm with a looping function to poll the status register. The SVF files do not have the capability to loop in a polling function, so the wait times will need to be expanded manually.

NOTE: This issue is inherent to the XC9500 series CPLDs and does not affect CoolRunner or PROM devices.

Xilinx recommendations for alternatives are:

IEEE 1532


AR# 20287
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article