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AR# 20289

6.3i IP Update 4 CORE Generator - What's New and Known Issues List: IP-DSP


This Answer Record contains "What's New" and "Known Issues" addressed in the 6.3i IP Update 4.

NOTE: IP Update 4 (IP4_G) is compatible only with ISE 6.3i.



3GPP TCC Encoder v1.0

- N/A (first release).

3GPP TCC Decoder v1.0

- N/A (first release).

Complex Multiplier v2.0

- Support added for Virtex-II,Virtex-II Pro, and Spartan-3. All families with embedded multipliers are now supported.

- Optimization in the Virtex-4 implementation results in better performance.

- Enhancements to more efficiently support larger input operand precision.

Fast Fourier Transform v3.1

- To download the xFFT v3.1 patch, please see (Xilinx Answer 20709).

- "Optimize for Speed Using XtremeDSP Slices" option in Virtex-4 enables operation of the core at higher clock speeds by utilizing more DSP48s. This provides you with an additional option for making trade-offs between resource utilization and performance.

- Maximum clock speed has been increased for all supported FPGA families.

MAC FIR v5.1

- Optimization of multi-MAC Engine filter implementations enable up to 35% reduction in resource utilization.

Reed Solomon Decoder v5.1

- Support for multi-channel implementation which improves core efficiency for high-speed applications such as OC-192.

- Updated puncturing option which improves core efficiency for standards such as IEEE802.16d.

- New self-recovery mode feature.

Viterbi Decoder v5.0

- Additional sel_output signal for Dual decoder Viterbi configuration allows users to identify whether the input data has been decoded in the dual decoder using decoder 0 or decoder 1.

- New features associated with Trellis Initialization and Direct Traceback provide users with additional ways to handle packets in the decoder.


LogiCORE 2-D DCT v2.0

- 2-D DCT VHDL Model simulates only at speeds higher than 100 MHz.

Please see (Xilinx Answer 20316).

LogiCORE 3GPP TCC Decoder v1.0

- Data sheet lists the incorrect number of BRAMs for the example design.

Please see (Xilinx Answer 20309).

LogiCORE 3GPP TCC Decoder v1.0, 3GPP TCC Encoder v1.0, xFFT v3.1

- Memory collisions when simulating the xFFT, 3GPP TCC Encoder, 3GPP Decoder when using VHDL and targeting Virtex-4.

Please see (Xilinx Answer 20314).

LogiCORE CIC v3.0

- The CIC v3.0 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input.

Please see (Xilinx Answer 12480).

- Resetting the CIC filter.

Please see (Xilinx Answer 20187).

LogiCORE Complex Multiplier v2.0

- Complex Multiplier v2.0 contains CR fix that should have been placed in the MAC FIR v5.1 Version Info file.

Please see (Xilinx Answer 20313).

- Complex Multiplier v2.0 Data Sheet overview lists wrong input and output bit widths.

Please see (Xilinx Answer 20308).

LogiCORE DA FIR Filter

- CORE Generator memory consumption issues occur with the DA-FIR.

Please see (Xilinx Answer 18663).

- Calculating the clock/pipeline latency of the DA FIR filter.

Please see (Xilinx Answer 4610).

LogiCORE DA FIR Filter (Possibly other cores as well)

- Verilog SimPrim X_SRLC16E reports an error where VHDL SimPrim X_SRLC16E reports only a warning.

Please see (Xilinx Answer 19518).


- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters.

Please see (Xilinx Answer 5366).

LogiCORE DDC v1.0, MAC FIR v5.0 DA FIR v9.0

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.

Please see (Xilinx Answer 14202).

LogiCORE DDC v1.0

- DDC can be implemented in the Spartan-3 and Virtex-II Pro devices.

Please see (Xilinx Answer 18937).

LogiCORE 32-pt Configurable FFT v3.0

- The output data appears to be in the wrong bin.

Please see (Xilinx Answer 18901).

LogiCORE 1024-pt FFTv1.0

- The block RAM configurations in the FFT/IFFT Data Sheet do not match the hardware configurations.

Please see (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0

- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT.

Please see (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0

- The FFT for a Virtex-II device causes PAR warnings and errors.

Please see (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0

- No Verilog model is available for the FFT Core.

Please see (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0

- The RESULT signal is not reset properly in the 64-point FFT v2.0.

Please see (Xilinx Answer 15383).


- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings.

Please see (Xilinx Answer 14861).


- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration).

Please see (Xilinx Answer 9288).

LogiCORE xFFT v3.1

- Information on Radix 2 or Radix 4 Burst mode output order.

Please see (Xilinx Answer 18825).

LogiCORE xFFT v3.1

- To download the xFFT v3.1 patch.

Please see (Xilinx Answer 20709).

LogiCORE xFFT v3.1, MAC FIR v5.1

- MAC FIR might require more resources than expected, due to routing limitations, when input bit widths are larger than 18 bits.

Please see (Xilinx Answer 20307).


- Information on support for multiple MAC FIRs with different COE files in the same project.

Please see (Xilinx Answer 16433).

- Back-annotated Verilog simulation causes memory collision errors.

Please see (Xilinx Answer 16106).

- MAC FIR Version Info File is missing CR fix.

Please see (Xilinx Answer 20313).

LogiCORE Multiplier Generator

- A Multiplier Generator Model fails to compile with Synopsys VCS.

Please see (Xilinx Answer 19520).

LogiCORE Multiplier Generator

- Virtex-4 simulation mismatches.

Please see (Xilinx Answer 20777).

LogiCORE Reed Solomon Encoder v5.0

- Information on the Ghost Enable pin in the GUI.

Please see (Xilinx Answer 19526).

AR# 20289
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article