Main

PAR, LogiCORE MAC FIR, FFT, FIR Compiler - Why do I receive "ERROR:Place:419", "ERROR:Place:341", or "ERROR:Place:665" when I try to place-and-route my MAC FIR or FFT in a Virtex-II/-II Pro, Spartan-3/-3E device?

AR# 20307

Search For Another Answer

Topic IP-DSP Horizontal
Last Updated 06/11/2008
Status Active
Description

Keywords: Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E CORE Generator, CORE, CORE Generator, generator, error, multipliers, block RAM, block RAMs, BRAM, BRAMs, MAC, FIR, xFFT, resources, Fast Fourier Transform, FIR Compiler

When I try to place-and-route my MAC FIR of xFFT, I receive the following errors, even though I have enough multiplier and block RAMs in my Virtex-II, Virtex-II Pro, Spartan-3, or Spartan-3E device:

"ERROR:Place:341 - The design contains 6 Block RAM components that are configured as 512x36 Block RAMs and 168 Multiplier components. The Multiplier site adjacent to the location of a 512x36 Block RAM component must remain free because of resource sharing. Therefore a device must have at least 174 Multiplier sites for this design to fit. The current device has only 168 Multiplier sites."

"ERROR:Place:419 - The design contains 16 BRAM components that are configured as 512x36 BRAMs and 16 multiplier components. The multiplier site adjacent to the location of a 512x36 BRAM component must remain free because of resource sharing. Therefore a device must have at least 32 multiplier sites for this design to fit. The currently chosen device has only 28 multiplier sites."

"ERROR:Place:665 - The design has 11 block-RAM components of which 11 block-RAM components require the adjacent multiplier site to remain empty. This is because certain input pins of adjacent block-RAM and multiplier sites share routing resources. In addition, the design has 22 multiplier components. Therefore, the design would require a total of 33 multiplier sites on the device. The current device has only 24 multiplier sites."

Solution

The "ERROR:Place:419", "ERROR:Place:341", or "ERROR:Place:665" message indicates that the design contains 20 block RAM components that are configured as 512x36 block RAMs and 40 multiplier components. The multiplier site adjacent to the location of a 512x36 block RAM component must remain free because of resource sharing. Therefore, a device must have at least 60 multiplier sites for this design to fit. The currently chosen device has only 44 multiplier sites.

This problem occurs because Virtex-II, Virtex-II Pro, Spartan-3, and Spartan-3E devices contain shared interconnects between the multipliers and the block RAMs. This means that the adjacent block RAM can be used only up to 18 bits wide when the multiplier is used.

If the device utilization report is examined, the error might seem incorrect.

Device utilization summary:
Number of External IOBs.................43 out of 396..........10%
Number of LOCed External IOBs.....0 out of 43..............0%
Number of MULT18X18s................40 out of 44............90%
Number of RAMB16s......................20 out of 44............45%
Number of SLICEs..........................1913 out of 4928.....38%
Number of BUFGMUXs..................1 out of 16................6%

In this design, 40 multipliers are used. This effectively means that the 40 associated block RAMs are not usable as in the design. Block RAMs that are 512x36 bit are required, which is why PAR reports the error.

There are several ways to work around this issue:
- Select a larger device.
- Reduce the input width to 18 so that the adjacent block RAM and multiplier can be used.
- Reduce number_of_stages_using_block_ram_for_data_and_phase_factors, so that the number of block RAM used would be reduced. (NOTE: This option increases the number of slices used.)

More information on resource limitations is available in the "Multiplier" section of Virtex-II Platform FPGA User Guide, or in the "Muliplier" section of the Spartan-3 Generation FPGA User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug002.pdf
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

Please See (Xilinx Answer 29209) for a detailed list of LogiCORE Fast Fourier Transform (FFT) Release Notes and Known Issues.
 
 
/csi/footer.htm