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AR# 20339

6.3 EDK - Simulation of a design which includes the OPB / PLB Ethernet Core fails

Description

Keywords: EDK, XPS, Ethernet, emac

Urgency: Standard

General Description:
A EDK design that includes the OPB / PLB Ethernet Core fails during the simulation in EDK 6.3.

The following error message in ModelSim appears:

# Loading C:/vhdl_libs/edklib/plb_ethernet_v1_01_a/.xemac(implementation)
# Loading C:/vhdl_libs/unisim/.emac(emac_v)
# ** Error: (vsim-3817) Formal port "clientemac0dcmlocked" declared in the entity is not in the component.
# Time: 0 ps Iteration: 0 Region: /testbench/fpga_top_inst/system_top/ethernet/ethernet/xemac_i/inst_emac File: C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd
# ** Error: (vsim-3817) Formal port "clientemac0pausereq" declared in the entity is not in the component.
# Time: 0 ps Iteration: 0 Region: /testbench/fpga_top_inst/system_top/ethernet/ethernet/xemac_i/inst_emac File: C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd
# ** Error: (vsim-3817) Formal port "clientemac0pauseval" declared in the entity is not in the component.
# Time: 0 ps Iteration: 0 Region: /testbench/fpga_top_inst/system_top/ethernet/ethernet/xemac_i/inst_emac File: C:/Xilinx/vhdl/src/unisims/unisim_SMODEL.vhd
# ** Error: (vsim-3817) Formal port "clientemac0rxclientclkin" declared in the entity is not in the component.

Solution

The problem is that in the emac is taken from the UniSim Library (new for Virtex-4) instead of the EDK Library. When using the following command line, ModelSim will take the wrong emac instance.

vsim -Lf unisim -t ps +notimingchecks +nowarn work.testbench_conf

When removing the -Lf unisim statement in the commandline, ModelSim will load the right emac instance.

vsim -t ps +notimingchecks work.testbench_conf
AR# 20339
Date Created 11/08/2004
Last Updated 04/11/2007
Status Archive
Type General Article