Keywords: optimization, pad
A pad was removed from my design during mapping and the Removed Logic section of the MAP Report (.mrp) claims that the input pad net was sourceless. How can this be? To understand this problem, it is important to define a few terms related to this issue:
Trimming is the removal of logic that is unused, either because it is undriven, unloaded, or because it feeds back on itself without affecting any of the chip's output logic.
Optimization is the removal of logic because it can logically be reduced to a simpler form such as a constant value. For example, a flip-flop that can never logically go High is reduced to a GND connection.
The Removed Logic section of the MAP Report attempts to explain why logic is removed for both trimming and optimization reasons. This is complicated by the fact that optimization can lead to trimming. For example, if a flip-flop is removed for optimization and the S/R signal driving the flip-flop has no other loads, that S/R signal is trimmed as a loadless signal.
For trimmed logic, the removed logic summary attempts to show the source of the trimming by listing it first and then listing any subsequent trimming indented in order on the next lines. In the following example, the trimming is alleged to begin at signal "adsS_855" because the signal has no source, but since this signal is driven by an input pad, this information is false.
Example
NOTE: The "." represents one level of indentation in the following example.
The signal "adsS_855" is sourceless and has been removed.
.Sourceless block "adsS_93779/DDR_IN/IBUF1" (BUF) removed.
..The signal "adsS_93779/DDR_IN/D_INT" is sourceless and has been removed.
...Sourceless block "adsS_93779/DDR_IN/FDRSE0" (SFF) removed.
....The signal "adsS_93779/q_w<7>" is sourceless and has been removed.
.....Sourceless block "adsS_93779/q_7" (SFF) removed.
......The signal "adsS_98365" is sourceless and has been removed.
.......Sourceless block "adsS_93779/q_5" (SFF) removed.
........The signal "adsS_98363" is sourceless and has been removed.
.........Sourceless block "adsS_93779/q_3" (SFF) removed.
..........The signal "adsS_98361" is sourceless and has been removed.
...........Sourceless block "adsS_93779/q_1" (SFF) removed.
............The signal "adsS_98423" is sourceless and has been removed.
.............Sourceless block "adsS_92885/adsS_92143/adsS_85796/adsS_77025/adsS_52661/adsS_1863" (ROM) removed.
..............The signal "adsS_92885/adsS_92143/adsS_85796/adsS_77025/adsS_52661/adsS_1869" is sourceless and has been removed.
Analysis of this circuit shows that the last signal in this list drives the CLR pin of an FDC that was optimized away because it had an INIT value of "0" and a constant clock signal. This optimization caused the CLR signal to be loadless and this entire sequence of trimming occurred because the logic is loadless rather than sourceless.
If you suspect that a flip-flop is optimized to a constant value because it never changes states, it can be useful to reverse the INIT value as a test to see if this affects the optimization and resultant trimming.
A CR has been filed and is under investigation to correct the misleading information about removed logic in the MAP report. Meanwhile, if this information does not appear to make sense, consider the possibility that the trimming sequence is listed in reverse order. Also, consider the effects that logic optimization can have on trimming.