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AR# 20362

EDK, DDR, Spartan-3 - "ERROR:MDT - opb_ddr (opb_ddr_0) - C:\system.mhs:217 - not supported for architecture 'spartan3'!"


General Description: 

When implementing a Spartan-3 EDK system using a OPB_DDR controller the following error occurs: 


"ERROR:MDT - opb_ddr (opb_ddr_0) - C:\system.mhs:217 - not supported for architecture 'spartan3'!" 


The data sheet notes that Spartan-3 is a supported architecture. Why does this error occur? What can I do to use DDR memory with Spartan-3 and EDK?


The official support for DDR SDRAM for Spartan-3 is scheduled for EDK 7.1 Service Pack 2 (2nd Quarter 2005). 


While the OPB_DDR controller is functionally correct, depending on the usage, it might not meet the minimum clock period of the DDR memory chosen (i.e., not meeting the internal FPGA timing in Spartan-3). Thus official support for the OPB_DDR was removed from the core at this time.  


Support for the DDR controller can be re-enabled manually. With slow memory clock frequency and through the efforts of design optimization, it might be possible to use the unsupported OPB DDR Core targeted to a Spartan-3 device: 


1. Copy the existing DDR controller from the EDK install area (typically C:\EDK\hw\XilinxProcessorIPLib\pcores) to a pcores directory. Create a pcores directory in the root of the project if one does not already exist.  

2. Modify the <myproject>\pcores\opb_ddr_v1_10_a\data\opb_ddr_v2_1_0.mpd. Modify the ARCH_SUPPORT option to contain spartan3, for example: 

OPTION ARCH_SUPPORT = qrvirtex2:qvirtex2:virtex2:virtex2p:virtex4:spartan3 

3. Save the file, restart XPS to reload the core, and rebuild the system. 

4. Verify that the valid timing constraints are applied to the system, and that those constraints are met in the PAR report or via Timing Analyzer. 


Note that the minimum frequency of the DDR RAM must be met for reliable operation. It might be helpful to choose a RAM device will a lower minimum frequency. Internal Xilinx timing constraints must also be met. Internal Xilinx timing may be improved by enabling the additional pipeline stages in the opb IPIF. 


To enable additional pipeline registers: 


1. Modify the <myproject>\pcores\opb_ddr_v1_10_a\hdl\opb_ddr.vhd file to a '7' (maximum) pipeline as below: 

-- IPIF pipeline model number 

constant PIPELINE_MODEL : integer := 7; 

2. Save the file and regenerate the hardware. Note that there will be additional latency through the OPB_DDR controller. 

3. Verify that static timing constraints are being met.

AR# 20362
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article