LogiCORE CORDIC v3.0 - Why does the simulation output of the CORDIC fail to update when the bit width is larger than 12 bits?
Description
Keywords: CORE Generator
Why does the simulation output of the CORDIC fail to update when the bit width is larger than 12 bits?
Solution
This issue is fixed in v4.0 and beyond.This is a known behavioral simulation problem.
Even when the input changes and ND signal are asserted, RDY will go High, but the OUTPUT might change to (or stay at) an incorrect value. This occurs only in behavioral simulation with an input width set to greater than 12 bits. It does not depend on the actual input data.
You can work around the problem by performing a Post-Translate simulation. For more information, see (Xilinx Answer 22333).
See (Xilinx Answer 29570) for a detailed list of LogiCORE CORDIC Release Notes and Known Issues.