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AR# 20414

LogiCORE Asynchronous FIFO and FIFO Generator - Limitations of the Behavioral Model

Description

Keywords: CORE Generator, Verilog, simulation, rd_en, wr_en, rd_clk, wr_clk, counter, clock, domains, synchronization

The behavioral models for Asynch FIFO and FIFO Generator are purely functional model. They do not model the behavior of the core on a clock cycle-by-cycle basis. Consequently, they may not reflect the exact behavior of the core in the hardware. Flags and counters might be updated simultaneously with the clocks in the behavioral simulation, and there might be a cycle or two of delay in the structural and gate-level simulation. See below for more specific characteristics of the model.

Solution

IMPORTANT NOTE:
Unlike behavioral models for other cores, Asynchronous FIFO and FIFO Generator behavioral models are FUNCTIONAL ONLY; they do not model the delays through the core. Consequently, you must consider the following points when comparing the behavioral model simulation to the other simulation (structural and gate-level) and the actual behavior of the core in the device:

- Write operations occur relative to the wr_clk clock domain, as do the corresponding handshaking signals.
- Read operations occur relative to the rd_clk clock domain, as do the corresponding handshaking signals.
- The delay through the FIFO (the time it takes for a write to be available on the read port) will differ between the behavioral model and the core.
- The delay between an operation and the corresponding update of the rd_count and wr_count signals will differ between the model and the core. The data count outputs should be used only to estimate the number of words in the FIFO and should never be used to determine a precise word count.
- The EMPTY and ALMOST_EMPTY outputs are correct relative to the rd_clk clock domain, but they might differ between the behavioral model and the core because of differences in latencies from the wr_clk domain.
- The behavior of the EMPTY output will differ between the behavioral model and the core. Since the EMPTY flag is considered a "pessimistic" flag, its behavior as the FIFO becomes EMPTY is well-defined. However, the behavior as data is written into an empty FIFO can vary. Consequently, the behavioral model and the core will behave similarly in that the EMPTY flag will go High when the last word is read in from the FIFO. However, because the latency from the wr_clk clock domain to the rd_clk clock domain will differ, the time at which the EMPTY flag is released is uncertain. (This applies to ALMOST_EMPTY as well.)
- The FULL and ALMOST_FULL outputs are correct relative to the wr_clk clock domain, but might differ between the behavioral model and the core because of differences in latencies from the rd_clk domain.
- The behavior of the FULL flag will differ between the behavioral model and the core. Since the FULL flag is a "pessimistic" flag, the behavior of FULL as the FIFO goes full is well-defined. However, the behavior as data is read out from a full FIFO can vary. Consequently, the behavioral model and the core will behave similarly in that the FULL flag will go High when the last word is written to the FIFO. However, because the latency from the rd_clk clock domain to the wr_clk clock domain will differ, the time at which FULL is released is uncertain. (This applies to ALMOST_FULL as well.)

Special Considerations
- The rd_count and wr_count are NEVER an exact representation of the number of words in the FIFO; these only estimate the number of words.
- The rd_count and wr_count will always be correct after a period of time, where RD_EN=0 and WR_EN=0. In another words, the rd_count and wr_count will reach the correct value some time after the read and write operation is suspended.

Alternative to Behavioral Simulation
Instead of running behavioral simulation, you can run structural simulation, gate-level simulation, or timing simulation as described in the Synthesis and Verification Design Guide. To run structural simulation, edit your Core Generator project settings to generate the structural simulation model. To generate a post-NGDBuild simulation model for an EDIF netlist generated from the CORE Generator, see the Verifying Your Design -> Running NetGen section of the Synthesis and Verification Design Guide accessible at:
http://www.xilinx.com/support/software_manuals.htm
AR# 20414
Date Created 11/29/2004
Last Updated 06/06/2006
Status Active
Type General Article