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AR# 20433

7.1i XST - "ERROR:Xst:872 - "file.v" line xx: Unsupported target."

Description


General Description:

The following error message:



"ERROR:Xst:872 - "file.v" line xx: Unsupported target."



refers to an unsupported assignment made during port mapping, reg assignment or wire assignment.

Solution


The above error message is generated if "index vector part select" is used:



module top (clk, idx, byte_inp, byte_out);

input clk, idx;

input [1:0] byte_inp;

output [1:0] byte_out;



reg [0 :3] vec ;



assign byte_out = vec[2*idx +: 1]; //ERROR:Xst:850



always @(posedge clk)

vec[2*idx +: 1] <= byte_inp ; //ERROR:Xst:872



endmodule





Using the example above, you can re-code without using "index vector part select":



Example 1:



module top (clk, idx, byte_inp, byte_out);

input clk, idx;

input [1:0] byte_inp;

output [1:0] byte_out;



reg [3:0] vec ;



assign byte_out = vec >> 2*idx ;

always @(posedge clk) begin

vec = byte_inp << 2*idx ;

end



endmodule



Example 2:



module top (clk, idx, byte_inp, byte_out);

input clk, idx;

input [1:0] byte_inp;

output [1:0] byte_out;



reg [3:0] vec ;



assign byte_out = idx ? vec[3:2]:vec[2:1];



always @(posedge clk)

begin

case (idx)

1'b0 : vec[1:0] <= byte_inp ;

default : vec[3:2] <= byte_inp ;

endcase

end



The above error message will occur if output ports are mistakenly connected to constant values during port mapping:



my_mod DUT(

...

.OUTPUTPORT(8'b00000000),

...

);



Either connect the output port to a signal:



my_mod DUT(

...

.OUTPUTPORT(my_sig),

...

);





or leave it open:



my_mod DUT(

...

.OUTPUTPORT(),

...

);
AR# 20433
Date Created 09/03/2007
Last Updated 02/13/2012
Status Archive
Type General Article