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AR# 20477

Spartan-3 Configuration - How do I create a 3.3V-tolerant configuration interface?


Keywords: Spartan-3, configuration, 3.3V, tolerant, diagram

The 3.3V-Tolerant Configuration Interface section of the Spartan-3 Functional Description Data Sheet specifies that it is possible to achieve 3.3V tolerance at the configuration interface simply by adding a few external resistors. Where do I add these resistors and what value should these resistors have?

The Spartan-3 Functional Description Data Sheet is linked at:


The Spartan-3 FPGA, like others, has dedicated and nondedicated configuration pins. The dedicated configuration pins include PROG_B, HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE and M0-M2. These dedicated pins are powered by VCCAUX (2.5V). The dual-purpose configuration pins include INIT_B, DOUT, BUSY, RDWR_B, CS_B and DIN/D0-D7. Each of these pins, depending on which bank they are in, are powered by either VCCO Bank 4 or VCCO Bank 5.

A 3.3V tolerance is implemented as follows:

First, to power the dual-purpose configuration pins, apply 3.3V to the VCCO_4 and (as needed) the VCCO_5 lines. This scales the output voltages and input thresholds associated with these pins so that they become 3.3V compatible.

NOTE: If your source (PROM, microprocessor, etc.) is a 3.3V device, meaning it transmits and receives 3.3V signals, the easiest solution is to power VCCO Banks 4 and 5 with a 3.3V source. If you have a 2.5V PROM, the easiest solution is to power VCCO bank 4 and 5 with a 2.5V source. These solutions leave you with the most straightforward connections and will limit the number of series resistors needed to achieve a 3.3V-tolerant solution.

Second, in order to power the dedicated configuration pins, apply 2.5V to VCCAUX. If a dedicated pin, such as CCLK, is being driven by a 3.3V signal, as the case may be in a slave configuration mode where CCLK is an input, a current-limiting series resistor is required to limit the reverse current to 10 mA or less. For more information on the voltage tolerance of the Spartan-3 I/O, see (Xilinx Answer 19146).

The following images depict different 3.3V-tolerant solutions for different configuration modes:

Black lines show normal connections.
Green lines from VCCAUX-powered output to VCCO-powered input.
- High logic level noise margin is reduced; a pullup resistor is recommended to ensure adequate noise margin.
Green lines from VCCO-powered outputs to VCCAUX-powered input.
- Reverse current will be driven into the VCCAUX rail and current will need to be limited to 10 mA or less through a series resistor (Rser)
Dotted green lines indicate optional DONE pull-up resistor.
- if DriveDone = No, the resistor is used
- if DriveDone = Yes, this resistor is not present

3.3V Master-Serial Configuration with 3.3V configuration source

Master-Serial Interface
Master-Serial Interface

3.3V Master-Serial Configuration with 3.3V and JTAG with Platform Flash Prom


3.3V Slave-Serial Configuration with 3.3V configuration source

Slave-Serial Interface
Slave-Serial Interface

3.3V Master Parallel Configuration with 3.3V configuration source

Master Parallel Interface
Master Parallel Interface

3.3V Slave Parallel Configuration with 3.3V configuration source

Slave Parallel Interface
Slave Parallel Interface

3.3V JTAG Configuration

3.3V JTAG Configuration
3.3V JTAG Configuration

In all of the above scenarios, Rser is equal to 56 Ohms. For more information on how to calculate the value of Rser, see (Xilinx Answer 20492).

For more information on how to make an I/O 5V tolerant, see (Xilinx Answer 19146).

It is recommended that you use a regulator or supply that can tolerate reverse current on the VCCAUX lines. However, if your supply or regulator cannot tolerate the reverse current, which is most likely the case with a low-cost power supply, a shunt resistor (Rpar) is recommended to divert the reverse current away from the regulator to maintain proper regulation. For more information on how to calculate the value of Rpar, see (Xilinx Answer 20496).

See also (Xilinx XAPP453): "The 3.3V Configuration of Spartan-3 FPGAs."
AR# 20477
Date Created 12/09/2004
Last Updated 12/11/2006
Status Active
Type General Article