A VHDL file is added to a project, and the following error occurs:
"ERROR:16 - <file_name>.vhd Line <##>. Circular hierarchy reference found. Breaking cycle at module 'or_tree'."
The file is eventually added to the Project Navigator and is synthesizable. However, every time the file is changed and then saved, the error message occurs.
The VHDL parser that Project Navigator uses is not able to handle Recursive VHDL. However, the error message occurs only the first time the file is saved. Project Navigator will correctly pass the VHDL file(s) to XST. XST is able to synthesize projects containing recursively called source files, as a recursive situation guarantees that the design unit being instantiated is already compiled.
See also (Xilinx Answer 19839).