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AR# 20491

7.1i CORE Generator - Known Issues and What's New for CORE Generator in the 7.1i design tools release

Description

Keywords: COREGen, notes

Urgency: Standard

General Description:
This Answer Record contains the Release Notes for CORE Generator 7.1i. The following information is included:
- Release Notes
- What's New in 7.1i
- Known Issues

Solution

1

Supported Operating Systems
- Windows 2000 Professional (Service Pack 2-4)
- Windows XP Home (Service Pack 1, 2) / Professional (Service Pack 1, 2)
- Sun Solaris 8/9
- Linux Enterprise 3.0

IP Updates for CORE Generator 7.1i
For information on the latest available CORE Generator IP updates, visit the Xilinx Download Center:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
Follow the instructions for downloading and installing these updates.


Acrobat Reader Requirement
To view core data sheets, Acrobat Reader Version 4 or later must be installed. You can download the latest Acrobat Reader software from the Adobe Web site:
http://www.adobe.com/products/acrobat/readstep.html

To search for available IP Cores, see Locator for IP Solutions at:
http://www.xilinx.com/xlnx/xebiz/search/ipsrch.jsp

If you have comments, questions, or problems, open a WebCase at:
http://www.support.xilinx.com/support/clearexpress/websupport.htm

2

IP Known Issues

7.1i - Known Issues for IP Cores (DSP, System Logic, Networking, Ethernet, System I/O)
See (Xilinx Answer 20486).

3

What's New

Cores Included in this Release
http://www.xilinx.com/ipcenter/coregen/coregen_iplist_71i.htm

Pre-compiled XilinxCoreLib libraries for ModelSim Xilinx Edition II (MXE) are available at:
http://www.support.xilinx.com/support/mxelibs/index.htm

CORE Generator Project files have a new format and file extension (.cgp). Existing CORE Generator project files (coregen.prj) can be opened and automatically converted in 7.1i. For details, see (Xilinx Answer 21103) - 7.1i CORE Generator - How to open and/or convert pre-7.1i COREGen project files (coregen.prj) in CORE Generator 7.1i or later.

4

General Known Issues
6.1i COREGen - CORE Viewer reports incorrect resource utilization for XST-based cores (Xilinx Answer 14676).
6.3i CORE Generator - "ERROR:NgdBuild:76" given for CORE Generator ".ngc" file (Xilinx Answer 20483).
7.1i CORE Generator - Some Core Viewer data, from footprint, is not readable (Xilinx Answer 20692).
7.1i CORE Generator - 'xlicmgr status' no longer returns full list of licenses. "ERROR:coreutil - Please use -c to specify feature name." (Xilinx Answer 20481).
7.1i CORE Generator - COREGen will not launch. Error messages: "Could not reserve enough space for object heap" and "Could not create the Java virtual machine" (Xilinx Answer 20708).
7.1i CORE Generator - COREGen returns message "ERROR:coreutil:195 - Could not create Java virtual machine" - JVM (Xilinx Answer 20780).
7.1i CORE Generator - "ERROR:sim:4 - Could not create clean working directory \\<unc_path>\myproj\tmp\_cg." (Xilinx Answer 20721).
7.1i CORE Generator - CORE Generator gives the message "Ignoring command: UNK." (Xilinx Answer 20695).
7.1i CORE Generator - COREGen core customization GUI appears to hang (Xilinx Answer 20720).
7.1i CORE Generator - COREGen Help and Online documentation do not work on Japanese platform (Xilinx Answer 20729).
7.1i CORE Generator - Creating a New Project yields the message "Could not create directory <dir_name>" (Xilinx Answer 20707).
7.1i CORE Generator - No IP is available for Automotive parts (Xilinx Answer 20765).
7.1i CORE Generator - The core view window shows multiple listings of IP Cores (Xilinx Answer 20479).
7.1i CORE Generator (Japanese version) - If the "_" (underscore) character is used in a component name, the character is written out as a "|" (pipe character). For details on this possible naming issue when using a machine with a Japanese 106-character keyboard, see (Xilinx Answer 15312).
7.1i CORE Generator - Error occurred while executing formal verification script "core2formal_wrp" (Xilinx Answer 20715).
7.1i CORE Generator - XCO file for block RAM components is not read correctly. Regeneration gives "ERROR:coreutil - Illegal combination: Port B Width invalid for Port A settings." (Xilinx Answer 21301)
AR# 20491
Date Created 12/10/2004
Last Updated 12/12/2006
Status Archive
Type General Article