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AR# 20524

6.3 EDK Install - Service Pack 2 Release Notes/README


Keywords: Unix, PC, Linux, software, update, SP1, 6.3i

Urgency: Standard

General Description:
This README Answer Record contains the Release Notes for EDK 6.3 Service Pack 2 (SP2), which include installation instructions and a list of the issues that are fixed by this Service Pack for the 6.3 release.



EDK 6.3i SP2 requires a valid ISE 6.3i SP2 or greater installation.

A successful installation of Xilinx EDK 6.3 SP2 updates your software version number to 6.3.2.

- The destination directory specified during the setup operation must contain an existing Xilinx EDK 6.3 installation. Only existing files will be updated.
- Set the Xilinx EDK 6.3 environment variable before commencing the installation of SP2.

Download installation instructions for PC users:
1. Download EDK_6_3_2_win.exe from:
2. Run "EDK_6_3_2_win.exe"

Download installation instructions for Solaris users:
1. Download EDK_6_3_2_sol.zip from:
2. Unzip EDK_6_3_2_sol.zip it into your $XILINX_EDK area

Download installation instructions for Linux users:
1. Download EDK_6_3_2_lin.zip from:
2. CD to the root of the 6.3 EDK installation
3. Run the following command:
/usr/bin/unzip <path to the EDK_6_3_2_lin.zip file>
4. When prompted to overwrite files, answer All


EDK Tool Related Solutions

6.3 EDK, PLB_EMC v2.00.a - Cannot run the program from external memory. See (Xilinx Answer 20227).

6.3 EDK - OPB/PLB 10/100 EMAC drivers for VxWorks do not support caching. See (Xilinx Answer 20276).

6.3 EDK - FlashWriter in XPS does not support PLB EMC peripheral. See (Xilinx Answer 20525).

6.3 EDK - FlashWriter fails when programming a file, at various offsets. See (Xilinx Answer 20548).

6.3 EDK, PLB_EMC v2.00.a, Library Generator - "ERROR:MDT - xget_handle SUBPROPERTY BUS : A NULL handle was provided." See (Xilinx Answer 20096).

EDK IP Related Solutions

6.3 EDK SP2- Processor IP Master Answer Record, How do I get the latest Processor IP status, releases, updates and patches? See (Xilinx Answer 20591).

OPB_ZBT - Incorrect timing of MEM_RW_N signal causes writes to ZBTs to fail. See (Xilinx Answer 20531).

EDK 6.3 - OPB_EMC 1.10.b input/output/3-state registers cannot be packed into IOBs. See (Xilinx Answer 20532).

EDK 6.3 - OPB_GPIO IP Core requires a large address space. See (Xilinx Answer 20533).

EDK 6.3 - PLB lockup when using the PLB IPIF V2_00_a IP Master interface ports. See (Xilinx Answer 20534).

EDK 6.3 - In opb2plb_bridge_v1_00_c, write immediately after read fails. See (Xilinx Answer 20535).

EDK 6.3 - In opb2plb_bridge_v1_00_c, interrupted burst write of odd number of words does not finish correctly. See (Xilinx Answer 20536).

EDK 6.3 - Found in opb_ipif_v2_00_h and opb_ipif_v3_01_a: Modify size of FIFO to/from IP signals to be based on generics. See (Xilinx Answer 20537).

EDK 6.3 - The function XSysACE_SectorRead in "xsysace_compactflash.c" does not issue CFGRESET. See (Xilinx Answer 20538).

6.3 EDK, opb_iic v1.01.c - Setting the parameter C_GPO_WIDTH to 0 generates "ERROR. See (Xilinx Answer 20539).

EDK 6.3 - GEMAC example code at "xgemac_example.h" uses misaligned buffer. See (Xilinx Answer 20540).

EDK 6.3 - In the ML310 BSB design, the IDSEL parameter of the OPB_PCI Core is incorrect. See (Xilinx Answer 20542).

EDK 6.3, OPB_IIC - System hangs when there are three IICs on the bus. One IIC communicates with other while the third IIC monitors the bus. See (Xilinx Answer 20419).
AR# 20524
Date Created 12/20/2004
Last Updated 04/12/2007
Status Archive
Type General Article