UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20529

Virtex-4 ES - All designs must be compiled in the ISE 7.1i Service Pack 1 or later and DCM requirement

Description

This answer record clarifies the following Virtex-4 FPGA Engineering Sample (ES) errata requirements which are documented in the official errata for each device:

NOTE: Errata items 1, 2, and 4 listed below are fixed in Virtex-4 FPGA Production devices. Errata item number 3 is not an issue for Step 1 and later XC4VLX and XC4VSX devices and SCD1 and later XC4VFX devices.

1. To use the DCM in High Frequency (HF) mode, designs must be compiled using ISE 7.1i Service Pack 1 (sp1) or later. For availability of the ISE 7.1i service pack, refer to: http://www.xilinx.com/support.

2. The DCM attribute CLKOUT_PHASE_SHIFT set to the value VARIABLE_CENTER is not supported.

3. If the only clock outputs used from a DCM are CLKFX and/or CLKFX180, and the input clock frequency (CLKIN) is outside of the CLKIN_FREQ_DLL_(HF or LF)_(MS or MR)_MIN/MAX range, use the macro in Solution #3 of this Answer Record to properly generate the LOCKED signal.

4. For source-synchronous applications, it is best to use the ChipSync features for the highest performance and lowest skew. If the DCM must be used, follow the guidelines outlined in this Answer Record to achieve a CLKIN_CLKFB_PHASE specification of +/-300 ps.

Virtex-4 FPGA Errata can be accessed at:
http://www.xilinx.com/support/documentation/virtex-4_errata.htm

The errata will clarify to which device the above requirements are applicable.

Solution

1. To use the DCM in High Frequency (HF) mode, designs must be compiled using ISE 7.1i Service Pack 1 (sp1) or later. For availability of the ISE 7.1i service pack, refer to: http://www.xilinx.com/support
This errata item requires of all Virtex-4 FPGAdesigns that you re-run MAP, PAR, and BitGen in ISE 7.1i Service Pack 1 or later.

Compiling Virtex-4 FPGA designs with previous ISE versions will not correctly configure the design to guarantee high-frequency DCM operation that meets all specifications.

NOTES:

- In FPGA Editor, unused DCMs will be marked as unused but configured as shown in Figure 1. This configuration can be safely ignored. Your DCM usage will be reported correctly in the MAP and PAR report.

Figure 1 - Unused DCM in FPGA Editor View
Figure 1 - Unused DCM in FPGA Editor View

2. The DCM attribute CLKOUT_PHASE_SHIFT set to the value VARIABLE_CENTER is not supported.

For Virtex-4 devices (as noted in the errata), using DCM(DCM_PS or DCM_ADV), the CLKOUT_PHASE_SHIFT value must NOT be set to VARIABLE_CENTER. Instead, use VARIABLE_POSITIVE or DIRECT.

For description and usage information of the CLKOUT_PHASE_SHIFT attribute, refer to the Virtex-4 User Guide at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides

3. If the only clock outputs used from a DCM are CLKFX and/or CLKFX180, and the input clock frequency (CLKIN) is outside of the CLKIN_FREQ_DLL_(HF or LF)_(MS or MR)_MIN/MAX range, use the macro below to properly generate the LOCKED signal.

Details of this item can be found in (Xilinx Answer 23624).

4. For source-synchronous applications, it is best to use the ChipSync features for the highest performance and lowest skew. If the DCM must be used, follow the guidelines outlined below to achieve a CLKIN_CLKFB_PHASE specification of +/-300 ps:

The following describes the steps required for DCM to achieve CLKIN_CLKFB_PHASE specification noted above:

a. For each IBUFG driving CLKIN/CLKFB input of a DCM, a global buffer (BUFG/BUFGCTRL) must be inserted between the IBUFG and CLKIN/CLKFB pin (see Figure 2). A single BUFG can drive multiple CLKIN pins of multiple DCMs.

Figure 2 - Insert BUFG between IBUFG and CLKIN/CLKFB
Figure 2 - Insert BUFG between IBUFG and CLKIN/CLKFB

b. Set environment variable XIL_DCM_BUFG_CLKIN before Place and Route (PAR). This environment variable will be supported in the ISE 7.1i Service Pack 1 or later.

UNIX Platform:

>setenv XIL_DCM_BUFG_CLKIN

PC Platform:

> set XIL_DCM_BUFG_CLKIN=1

AR# 20529
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4