The registers in the OPB_EMC and the PLB_EMC, pushed outside of the IOBs, which causes reasonable offset-out-after constraints to fail.
The input register resets are qualified in "emc.vhd" by input_datareg_rst. Because this signal is not the same as the 3-state and output register reset signals (Bus2IP_Rst), these registers cannot share the IOB so one of the two is left outside and that makes it fail timing.
The reason that the 3-state registers cannot be pushed into the IOB is because the registers are optimized down to one register and all of the 3-state lines are driven from the one slice register. A save attribute will probably keep XST from doing this optimization.
This has been fixed in emc_common_v2_00_a, which is included in OPB_EMC_V2_00_A.
This problem is fixed in the latest 6.3 EDK Service Pack, available at:
The first service pack containing the fix is EDK 6.3 Service Pack 2.