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AR# 20557

6.3 EDK - MicroBlaze mapping error - "ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=R-4C14.S1)"

Description

Keywords: UCF, User Constraints File

Urgency: Standard

General Description:
How do I fix the following mapper error with a MicroBlaze design?

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0,
RLOC=R-4C14.S1) which require the combination of the following
symbols into a
single SLICE component:
RAM symbol

"microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I23/PC_OF_Buffer"
(Output Signal = microblaze_0/microblaze_0/PC_OF<23>)
FLOP symbol
"microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I22/PC_EX_DFF"
(Output Signal = microblaze_0/microblaze_0/PC_EX_i<22>)
FLOP symbol
"microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I23/PC_EX_DFF"
(Output Signal = microblaze_0/microblaze_0/PC_EX_i<23>)
RAM symbol

"microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I22/PC_OF_Buffer"
(Output Signal = microblaze_0/microblaze_0/PC_OF<22>)
The clock enable signals don't agree. Please correct the design
constraints
accordingly.
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0,
RLOC=R-14C14.S1) which require the combination of the following
symbols into
a single SLICE component:
FLOP symbol"

The bits where this error message occurs might vary. The problem occurs because the tools split the signal that goes to the clock enable into two different signals, and the design tries to constrain these two clock enable signals into the same slice.

Solution

This issue will be fixed in a new version of MicroBlaze in the XPS (EDK) 7.1 release, which requires a change in the ISE 7.1 release.

To allow the mapper to complete, please add the following constraint to the system User Constraints File (UCF):

INST "microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I*" USE_RLOC=FALSE;

The "microblaze_0/microblaze_0" will depend on the MicroBlaze instance name in the design.

This relaxed constraint might reduce the Fmax of your design. If you want to be more selective, you can remove only the RLOCs for the bits and PC_EX_DFF that generate the errors. Instead of the above constraint, you can include the following constraints in your system UCF file:

INST "microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I2/PC_EX_DFF" USE_RLOC=FALSE;
INST "microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I3/PC_EX_DFF" USE_RLOC=FALSE;
INST "microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I22/PC_EX_DFF" USE_RLOC=FALSE;
INST "microblaze_0/microblaze_0/Data_Flow_I/PC_Module_I/PC_Bit_I23/PC_EX_DFF" USE_RLOC=FALSE;
AR# 20557
Date Created 12/28/2004
Last Updated 04/12/2007
Status Archive
Type General Article