What is the minimum and maximum input frequency for the clock divider?
The clock divider is not PLL or DLL based, so there is no minimum clock frequency nor is a constant clock source required.
The minimum input of the parameter global clock pulse width, High or Low (TCW), is defined. These minimum inputs are then used to determine a minimum cycle time and frequency.
For example :
XC2C256-7 Tcw = 2.2ns
The maximum clock divider input frequency = 1/(2.2ns + 2.2ns) = 227 MHz