We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 206

Synopsys Design Compiler - "Report_timing" asks for Design Time, technology license.


Keywords: report_timing, report, timing, Design Time, technology license

Urgency: Standard

General Description:
When I execute a "report_timing" command, the Design Compiler issues an
error such as:

Error: Unable to obtain a "Design Time" or technology license.


This error does not occur if you have either an FPGA Compiler license or a Design
Time license. This was a bug in Synopsys version 3.0b that was fixed in 3.0c.

This error only occurs if you have the following license:
Design Compiler with FPGA Option

AR# 206
Date Created 09/20/1995
Last Updated 04/04/2001
Status Archive
Type General Article