Does the PCI Express Core use the BREFCLK or BREFCLK2 inputs? How do I specify which input the core should use?
The PCI Express Core requires a 125 MHz input clock to produce a link rate of 2.5 gigabytes. The FPGA requires that this clock be input on certain pins so that the clock signal can use dedicated device routing resources to clock the RocketIO blocks. Each RocketIO has a BREFCLK and a BREFCLK2 input, and each input requires a different set of pins on the device based on the package being used.
For more information on the BREFCLK/BREFCLK2 pin locations, refer to Module 4 of the Virtex-II Pro Data Sheet under the section "BREFCLK Pin Definitions (RocketIO Only)." The Virtex-II Pro Data Sheets are located at: http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-II+Pro&iLanguageID=1
Because the RocketIO interfaces are contained within the PCI Express Core, you cannot directly switch between using the BREFCLK and BREFCLK2 interfaces. To select the input that is convenient for your board design, Xilinx provides two core files: one uses BREFCLK, and the other uses BREFCLK2.
The actual PCI Express Core is provided in an NGO format. A one-lane version and a four-lane version of the core are available if you have downloaded the PCI Express Core. Xilinx provides two NGO files for each version of the core, one for using BREFCLK and the other for using BREFCLK2. These files are located in the following directories as shown in Figure 1:
1x PCI Express Core
4x PCI Express Core
Does it matter which clock input is used?
No, the same performance can be achieved regardless of whether the BREFCLK or BREFCLK2 inputs are used.
Does it matter on which side of the device the clock pins are placed?
Yes, it does. The BREFCLK/BREFCLK2 input pins selected must be on the same side of the device as the RocketIO blocks that are used by the PCI Express Core.
Xilinx provides an example UCF file for use with the PCI Express Core. Can I deviate from this suggested pin-out?
Yes, you can change the pin-out, but you must follow these guidelines:
Using the 1x Core
When you use the 1x Core, ensure that the RocketIO block and the BREFCLK/BREFCLK2 input pins are on the same side of the device. Do NOT try to route the clock input across the device by placing the RocketIO block on the opposite side of the device from the clock inputs; this will not work. For more information, refer to the RocketIO Transceiver User Guide at:
Select "See All User Guides" to access the RocketIO User Guide.
Using the 4x Core
When you use the 4x Core, ensure that the four RocketIO blocks and the BREFCLK/BREFCLK input pins are on the same side of the device. You can select the order of the RocketIO blocks for the individual lane assignments. Xilinx recommends that the lanes be placed in order as 0, 1, 2, 3 or 3, 2, 1, 0 to meet timing closure and ease board layout. On devices with eight RocketIO blocks across the edge of the device, you can choose to use four blocks in succession or skip blocks.
Does the core use a DCM, and if so, does it matter where it is located?
Yes, the core uses one DCM to create the RocketIO Tx and Rx user clocks. The DCM should be located on the same side of the device as the BREFCLK/BREFCLK2 clock input and RocketIO blocks.
Will the core support Virtex-4 devices?
The PCI Express Core is currently being ported to Virtex-4 and will be available soon. For more information, contact your local FAE or sales representative.