When generating SPI4.2 v7.1 core, it allows you to select bank 9 or 10 for the Source core I/O Placement.
If you are targeting Virtex-4 device using FF672 package, you may get an error in MAP indicating that there is
not enough bonded I/O available.
When using FF672 package, banks 9 and 10 have only 16 bonded I/O, which is not enough to place all 18 pairs of LVDS signals (16 TDat + 1 TDClk + 1 TCtl ). It is recommended that you move TDat, TDClk, and TCtl to either bank 7 or 8 by editing the UCF file.
As mentioned in the SPI4.2 User Guide, the core does not require pin lock and therefore can be targeted to different banks. You will need to change the Source core AREA constraints to match the new I/O bank placement.
Please see the Constraining the Core section of the User Guide for more information.