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AR# 20606

7.1i MAP - New option for Virtex-4 flows: Global Optimization (-global_opt on)


Keywords: synthesis, sp1, subroutine, MAP, map, 7.1i, optimization, timing, global_opt

Urgency: Standard

General Description:
A new option has been added in MAP version 7.1i Service Pack 1: Global Optimization. What is it all about?


This subroutine is designed to improve the overall quality of results of designs. It is enabled by setting the "-global_opt on" option on the command line, or by selecting the "Global Optimization" option in the MAP Properties dialog in ISE. Once enabled, two other option can be enabled: Retiming ("-retiming on" on the command line) and Equivalent Register Removal ("-equivalent_register_removal on" on the command line).

For many flows, the NGD file that is produced by the Translate (NGDBuild) step of implementation represents the first time that the entire design is assembled. IP cores have been pulled in, subnetlists have been merged together, constraints have been annotated. The Global Optimization routine looks at this complete design to see if combinatorial logic can be reoptimized to run faster. Register optimizations are also performed; equivalent registers can be optimized away, and a register retiming stage is run to balance delays between registers. All of these features have been put in place to attempt to improve the maximum frequency of your clocks. These features may have been run during synthesis, but perhaps the entire design was not available for consideration.

Global Optimization is different from Timing Driven Packing and Placement (-timing) in that Global Opt is done purely on the logical database, whereas -timing concentrates on the physical implementation of the design. Global Opt currently allows for more netlist modification, but -timing considers packing and placement information. Both of these flows can be enabled at the same time, and both should provide improvements for the user.

Detailed Information:
This flow supports Virtex-4 devices only. No plans are in place to support older architectures, but Xilinx expects to support newer architectures in future releases. An error is issued if older architectures are targeted with this option. There are no restrictions on design source.

Here are the rules for other options (defaults in CAPS) that might or might not be used with Global Optimization:
-- The -l and -u switches are not allowed.
-- -retiming [on/OFF] and -equivalent_register_removal [ON/off] are supported once -global_opt is enabled.
-- All other MAP switches (including -timing and -ignore_keep_hierarchy) are supported.

It is recommended that Guide flows not be used with Global Optimization, because of the optimizations done. Xilinx also recommends that Incremental and Modular flows be avoided with this release. Guide Mode "Incremental" is explicitly prohibited.

The only indications that Global Optimization is being run are that the "-global_opt on" switch is listed in the command line in the ".mrp" file, and the note "Running global optimization..." is shown in the std out. An extra process is being run, so you should expect runtime to increase.

If errors occur within global optimization, you will see the following general error:
"Error: Map 128 - Unable to run global optimization for the design. Please rerun Map with global optimization disabled."
This error is shown only when an unrecoverable situation arises within the global optimization phase. Rather than provide cryptic information to you, you are asked to re-run MAP without this non-essential option.

Finally, the new Pin Preassignment feature is not supported with Global Optimization. The following errors could indicate the Pin Preassignment feature is used:

"ERROR:LIT:96 - IPAD symbol "<my_port>" is unconnected."
"ERROR:LIT:275 - IPAD IPAD symbol "<my_port>" is not connected to an IBUF, IBUFDS, GT11, GT11CLK, or MONITOR, those are the only legal components that can directly connect to an IPAD."
AR# 20606
Date Created 01/12/2005
Last Updated 08/25/2005
Status Active
Type General Article