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AR# 20615

LogiCORE Pipelined Divider v3.0 - I cannot find the Verilog behavioral simulation model for the Pipelined Divider; when performing a Verilog behavioral simulation, I receive "Error: (vsim-3033) ... The design unit was not found"


Keywords: CORE Generator, VSIM, template, VEO

I generate a Pipelined Divider using the Verilog flow, and the VEO template file is created. However, I cannot find a Verilog simulation model. Why? Also, why does the following error occur when I perform a Verilog behavioral simulation?

"Error: (vsim-3033) ... The design unit was not found"

When I perform a Verilog behavioral simulation of the Pipeline Divider Core v.3.0, the following error occurs:

"Error: (vsim-3033) divider_pipe.v(81): Instantiation of 'SDIVIDER_V3_0' failed. The design unit was not found.
# Region: /top_test_toplevel_v_tf/uut/divider_pipe
# Searched libraries:
# C:\Modeltech_xe58\win32xoem/../xilinx/verilog/xilinxcorelib_ver
# C:\Modeltech_xe58\win32xoem/../xilinx/verilog/unisims_ver
# work"

However, CORE Generator produces a Verilog wrapper file for simulation purposes (*.v file). Why does this occur?


The Pipelined Divider does not have a Verilog behavioral model. The supported language for behavioral simulation is VHDL. If your simulator does not support multiple languages, you can work around this issue by generating a Verilog structural model with ISE 7.1i or above.

For more information, please see (Xilinx Answer 22333).
AR# 20615
Date Created 09/04/2007
Last Updated 03/02/2008
Status Archive
Type General Article