UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20616

LogiCORE SPI-4.2 (POS-PHY L4) v7.1 - Compilation errors on Verilog design example testbench when using MTI v6.0

Description

General Description:

When compiling the Verilog design example testbench files by running the "simulate_mti.do" file or by compiling them individually, the simulator gives compilation errors. MTI simulator v6.0 gives the errors mentioned below. The actual compilation errors might differ from other simulators.

"# Compiling Test Bench Verilog

# ** Error: pl4_clk_gen.v(110): near "ps": expecting: ',' ';'

# ** Error: pl4_clk_gen.v(111): near "ps": expecting: ',' ';'

# ** Error: pl4_clk_gen.v(112): near "ps": expecting: ',' ';'

# ** Error: pl4_clk_gen.v(160): near "ns": expecting: ')'

# ** Error: pl4_startup.v(60): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_procedures.v(56): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_stimulus.v(59): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase.v(63): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_data_monitor.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_status_monitor.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_demo_testbench.v(88): Compiler directive `timescale is not allowed inside a module.

# ** Error: pl4_testcase_pkg.v(58): Compiler directive `timescale is not allowed inside a module.

# ** Error: G:/tools/modelsim/6.0/win32/vlog failed.

# Error in macro ./simulate_mti_timelimit.do line 27"

Solution

You might not see the errors if you are using MTI simulator v5.x or earlier. MTI v6.0 syntax checker has become more strict, hence these errors can now be seen.

"Two files need to be modified:

<...>/test/verilog/pl4_clk_gen.v

<...>/test/verilog/pl4_stimulus.v "

A) For pl4_clk_gen.v file, there are 2 changes (delete "ps" and "ns"):

1. Line 110-113, change from:

parameter TDClkPeriod = 2860 ps;

parameter RDClkPeriod = 2860 ps;

parameter UserClkPeriod = 5710 ps;

to

parameter TDClkPeriod = 2860 ;

parameter RDClkPeriod = 2860 ;

parameter UserClkPeriod = 5710 ;

2. Line 160, change from:

forever #(2.5 ns) SnkIdelayRefClk = !SnkIdelayRefClk;

to

forever #(2500) SnkIdelayRefClk = !SnkIdelayRefClk;

B) For pl4_stimulus.v file, there are 2 changes (adding for-loop):

1. Add the following declaration in line 340:

integer i;

2. Line 743-744, change from:

TCDatFF <= #`TFF {1024{1'b0}};

TCCtlFF <= #`TFF {1024{1'b0}};

to

for (i=0; i <= 1023; i = i+1)

begin

TCDatFF[i] <= #`TFF {19{1'b0}};

TCCtlFF[i] <= #`TFF {1{1'b0}};

end

AR# 20616
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article