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6.3.p03 System Generator for DSP - Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

AR# 20624

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Topic SysGen
Last Updated 01/14/2005
Status Active
Description

Keywords: SysGen, MATLAB, Simulink, delay, retiming, Verilog, simulation, mismatch

Urgency: Standard

General Description:
Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

Solution

This has been fixed in System Generator 6.3.p03.

http://www.xilinx.com/products/software/sysgen/sg_intro.htm
 
 
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