UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20624

6.3.p03 System Generator for DSP - Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

Description

General Description: 

Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

Solution

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20624
Date Created 09/03/2007
Last Updated 05/19/2014
Status Archive
Type General Article