UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20667

7.1i / 6.3i EDK - Which core should I use for connecting my external memory (SDRAM, DDR SDRAM, Flash, etc.) to the OPB or PLB bus?

Description

I want to connect an external memory to the OPB or PLB bus. Which core should I use?

Solution


The core to be used is dependent upon the external memory type and whether you want to connect the external memory to the PLB bus or the OPB bus.



SRAM, ZBT RAM and Flash memory should be connected to the OPB bus using the OPB EMC controller.

This core can be identified in EDK as OPB_EMC.



SRAM, ZBT RAM and Flash memory should be connected to the PLB bus using the PLB EMC controller.

This core can be identified in EDK as PLB_EMC.



SDRAM should be connected to the OPB bus using the OPB SDRAM controller.

This core can be identified in EDK as OPB_SDRAM.



SDRAM should be connected to the PLB bus using the PLB SDRAM controller.

This core can be identified in EDK as PLB_SDRAM.



DDR SDRAM should be connected to the OPB bus using the OPB DDR SDRAM controller.

This core can be identified in EDK as OPB_DDR.



DDR SDRAM should be connected to the PLB bus using the PLB DDR SDRAM controller.

This core can be identified in EDK as PLB_DDR.



If a SystemACE module is present in the system, it is possible to connect the module and associated Flash memory to the OPB bus.

The relevant core can be identified in EDK as OPB_SYSACE.



The data sheet for each core can be found in the following location:



<EDK_Installation_Directory>hw\XilinxProcessorIPLib\pcores\<core_name_vx_yy_z>\doc, where x_yy_z represents the core version.
AR# 20667
Date Created 09/04/2007
Last Updated 05/15/2012
Status Archive
Type General Article