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AR# 20668

9.1i EDK, OPB2PCI Bridge v1.00.c - How should constraints generated by the PCI UCF Generator be correctly applied to a design containing the OPB2PCI Bridge?

Description

The OPB2PCI Bridge Data Sheet states the following: 

 

"The IPIF/V3 bridge utilizes the LogiCORE PCI64 v3.0 Core that requires a ucf-file to meet PCI specifications. The ucf-file is available from LogiCORE Lounge and can be generated for the user's device of choice. This LogiCORE PCI64 v3.0 Core specific ucf-file must be included in the top-level ucf-file by the user...." 

 

How should these constraints be generated and correctly added into the system UCF file?

Solution

When using the LogiCORE PCI64 Core that is contained in the OPB2PCI bridge, constraints must be added to the system UCF file to ensure that the PCI Core will function correctly. 

 

The UCF Generator, available from the PCI Lounge (http://www.xilinx.com/pci) will generate example constraints appropriate for each supported device and package combination. 

 

The UCF generator will provide a variety of constraints including pin constraints, placement constraints, and timing constraints. 

 

The pin constraints in the example UCF file should be correlated with the appropriate inputs and outputs of the OPB2PCI Bridge, and the OPB2PCI Bridge external I/O should then be constrained accordingly in the system UCF file. 

 

Most of the timing constraints (e.g., period constraints, timing group definitions, offset in, offset out, etc.) are relatively straightforward to apply to the system UCF file. 

 

If global clock buffers are constrained in the example UCF file, the user will have to account for and constrain these in accordance with the design's clocking scheme. 

 

Many of the constraints will be provided in the following format: 

 

PCI_CORE/xyz/xyz/... 

 

Assuming that the OPB2PCI Core is named as "opb_pci_0" in the MHS file, these constraints should be copied and added to the system UCF file as follows: 

 

opb_pci_0/opb_pci_0/PCI_CORE/xyz/xyz/... 

 

E.G.: 

 

NET "PCI_CORE/CBE_IO<2>" IOBDELAY = BOTH ; 

INST "PCI_CORE/PCI_LC/PAR/OFD" IOB = TRUE ; 

INST "PCI_CORE/PCI_LC/E/LOWER/T0" LOC = "TBUF_X66Y27" ; 

INST "PCI_CORE/PCI_LC/MASTER/REQ/REQ1" LOC = "SLICE_X66Y46" ; 

INST "PCI_CORE/XPCI_ADQ0" TNM = FFS:PCI_FFS_ICE ; 

INST "PCI_CORE" TNM = FFS:PCIM_FFS ; 

 

would become: 

 

NET "opb_pci_0/opb_pci_0/PCI_CORE/CBE_IO<2>" IOBDELAY = BOTH ; 

INST "opb_pci_0/opb_pci_0/PCI_CORE/PCI_LC/PAR/OFD" IOB = TRUE ; 

INST "opb_pci_0/opb_pci_0/PCI_CORE/PCI_LC/E/LOWER/T0" LOC = "TBUF_X66Y27" ; 

INST "opb_pci_0/opb_pci_0/PCI_CORE/PCI_LC/MASTER/REQ/REQ1" LOC = "SLICE_X66Y46" ; 

INST "opb_pci_0/opb_pci_0/PCI_CORE/XPCI_ADQ0" TNM = FFS:PCI_FFS_ICE ; 

INST "opb_pci_0/opb_pci_0/PCI_CORE" TNM = FFS:PCIM_FFS ;

AR# 20668
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article