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AR# 20719

Virtex-II Pro RocketIO - When is RXCHECKINGCRC asserted after receiving the EOF?


When is RXCHECKINGCRC asserted after the EOF is received?


Regardless of RXDATAWIDTH, the latency is 4-5 RXUSRCLK cycles.  


This is not exact, as a clock domain crosses from RXRECCLK to RXUSRCLK; although it is always exact in simulation, there is a possibility of phase offset between RXRECCLK and RXUSRCLK.

AR# 20719
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article