UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20746

6.3 System Generator for DSP - Why I meet error when using Boolean signal to drive clk_sel pin of HW co-sim block?

Description

General Description: 

When I perform Hardware Co-simulation, I want to change the clock type to "Select from Input Port." According to the User Guide, I use a Boolean signal to drive the clk_sel pin. But an error appears during simulation: 

 

"S-function should set the data type of input port 3 of 'cosimtest/CoSimTest hwcosim' to the data type specified by the input argument of method mdlSetInputPortDataType. "

Solution

The clk_sel should be driven by double signal. After you remove GatewayIn block, then it can be simulated correctly. 

 

This has been addressed in System Generator for DSP 7.1. Please see the Hardware in the Loop Co-Simulation Documentation for more information.

AR# 20746
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article