UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20748

9.1i EDK - PLB_DDR v1.11a - How much memory space can the DDR SDRAM Controller cover?

Description

I am working with EDK and I have a large scale application program requiring large capacity DDR SDRAM, but I cannot find the possible maximum memory size. How do I attach a large DDR memory on a PLB bus?  

 

In the BSB environment, the DDR controller covers 512 MBytes. Is it possible to attach more than 512 MBytes?

Solution

See the PLB_DDR Data Sheet "PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller" -> "DDR SDRAM Controller Design Parameters". You can find the "plb_ddr.pdf" on your local PC: 

%XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\plb_ddr_v1_11_a\doc 

 

NOTE: C_DDR_AWIDTH + C_DDR_COL_AWIDTH + C_DDR_BANK_AWIDTH + log2(C_DDR_DWIDTH/8) must be < C_PLB_AWIDTH-1. 

 

The DDR controller can cover up to 1 GBytes memory space because the C_PLB_AWIDTH is 32. This depends on the DDR SDRAM memory that you selected. Make sure to confirm that the DDR SDRAM memory you selected can support this configuration. 

 

Note that in the BSB environment, the DDR controller-covered address should be related with the target board; this is determined by the board, rather than by DDR controller.

AR# 20748
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article