7.1i IP Update 1 CORE Generator - IP-DSP What's New and Known Issues List
Description
Keywords: ISE, CORE, CORE Generator, CORE Generator, Binary Counter, Comparator, Complex Multiplier, Distributed Arithmetic FIR Filter, DVB S2 FEC Encoder, FFT, Floating-point Cores, MAC, MACC, Pipelined Divider, RAM-based Shift Register, TCC Encoder 3GPP, LogiCORE
This Answer Record contains IP-DSP "What's New and Known Issues" addressed in the 7.1i IP Update 1.
Solution
1
WHAT'S NEW in 7.1i IP UPDATE 1Binary Counter v8.0
New Features in v8.0
- Support added for Virtex-4
- Support added for ISE 7.1i
- Area and speed improvements
- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models
- New addsub used to optimize bypass and constant count cases
Comparator v8.0
New Features in v8.0
- Support added for Virtex-4
- Support added for ISE 7.1i
- Area and speed improvements
- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models
- Pipelining option added
Complex Multiplier v2.1
No New Features in v2.1
Bug Fixes in v2.1
- The slice estimates have been removed from the GUI
- CR 185341: Simulation mismatch between behavioral model and netlist when optimization is for number of XtremeDSP Slices
- CR188289: The VHDL behavioral references the following libraries which are no longer legal:
--IEEE.STD_LOGIC_ARITH.ALL;
--IEEE.STD_LOGIC_SIGNED.ALL;
- CR 188655: The slice estimate in the information section of the cmpy_v1_0 GUI is off
- CR 193125: The information displayed in the Information Panel is incorrect
- CR 196678: Simulation mismatch between behavioral model and netlist
- CR 197555: GUI operand widths differ from data sheet
- CR 201720: The core cannot be generated using operands 35xN (18<N<36), optimization for number of XtremeDSP Slices
- CR 204409: The core cannot be generated using operands 35xN (N<18), optimization for number of XtremeDSP Slices
Distributed Arithmetic FIR Filter (DA FIR) v9.0
New Features in v9.0
- Support added for Virtex-4
Bug Fixes in v9.0
- CR 184935: Problem with "Invalid Value for Clock Cycles Per Sample" error caused by Customization GUI allowing invalid values for the "Clock Cycles/Output" Sample setting
- CR 199823: DA FIR-CORE Generator should check that every other coef is 0 for interpolating 1/2 band
DVB S2 FED Encoder v1.0
New Features in v1.0
- First release
Fast Fourier Transform (xFFT) v3.1
New Features in v3.1
- "Optimize for Speed Using XtremeDSP Slices" option in Virtex-4 enables operation of the core at higher clock speeds by utilizing more DSP48s. This provides you with an additional option for making trade-offs between resource utilization and performance
- Maximum clock speed has been increased for all supported FPGA families
Bug Fixes in v3.1
- CR 199541 - Incorrect FFT output results for Radix-4 Burst I/O when using Virtex-4
- CR 201500 - Core will not generate for Radix-4 Burst I/O and Radix-2 Minimum Resources when output width = 35 bits with phase factor width = 20 or 24 bits and for Pipelined Streaming I/O when output width > 35 bits with phase factor width = 20 or 24 bits
- CR 201885 - At the very beginning, Radix-4 Burst I/O and Radix-2 Minimum Resources will not begin processing when START is asserted unless SCLR is asserted first
Floating Point Cores v1.0
Features in v1.0
- First release
- IEEE-754 compliant floating-point operators with only minor documented deviations
- Can be configured for high-speed operation with an instruction issued on every clock cycle
- Supports add/subtract, multiply, divide and square-root operations, with a range of standard and non standard sizes, including single and double precision
- Support for Virtex-4 DSP48 feature
- Includes multi-cycle divide and compare operations for single precision
- VHDL behavioral model
- Core can be generated directly from a VHDL instantiation with XST transparently calling CORE Generator
MAC v4.0
New Features in v4.0
- Support added for Virtex-4
Pipelined Divider v3.0
New Features in v3.0
- Support added for Virtex-4
- Addition of Clock Enable (CE), Asynchronous Clear (ACLR), and Synchronous Clear (SCLR) inputs (also required for System Generator support)
- Addition of Ready for Data output (RFD)
- Reduced latency compared to V2.0
- Reduced area compared to V2.0
Bug Fixes in v3.0
- CR 131510: "Signed" and "Fractional" columns are switched in latency table in the data sheet
- CR 154089: Clarify how to use the core with multiple clocks per division option, clarify ambiguity in data sheet regarding latency
- CR 155250: Clocks per division still appears to be "1" in Verilog functional simulation model when multiple clocks per division is specified
- CR 175806: Inconsistent latency observed between functional and timing simulation models following reset. Add clarification regarding which clock the data is picked up at
- CR 179608: Divider gives incorrect result for some numbers (clarify supported dividend range)
- CR 186444: Negative Bus index error in Verilog simulation model
- CR 186445: Latency of core appears to disagree with data sheet and behavioral model
- CR 186501: Module outputs go to 'X' for too long following reset
RAM-based Shift Register v8.0
New Features in v8.0
- Support added for Virtex-4
- Support added for ISE 7.1i
- Area and speed improvements
- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models
- Pipelining for variable length cases implemented for a significant increase in performance
3GPP Turbo Convolutional Encoder v2.0 (TCC Encoder 3GPP v2.0)
New Features in v2.0
- New, more efficient interleaver enables 40% area reduction over v1.0 implementation
- External RAM option added
- Single-buffered option removed
Bug Fixes in v2.0
- Double buffering output now independent of FD (refer to data sheet for details)
2
KNOWN ISSUES in 7.1i IP UPDATE 1LogiCORE Binary Counter v8.0
- Mismatch between behavioral and timing simulation on the THRES0 output. See (Xilinx Answer 21411).
- Mismatch between behavioral and timing simulation on the Q output. See (Xilinx Answer 21412).
- Binary Counter does not generate when I enter the data in Hex and step size of greater than 10. See (Xilinx Answer 21413).
LogiCORE Complex Multiplier v2.1
- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).
LogiCORE Distributed Arithmetic FIR Filter (DA FIR) v9.0
- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).
- Interpolating Half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840)
LogiCORE Fast Fourier Transform (xFFT) v3.1
- Virtex-4 speed numbers in the data sheet are incorrect. See (Xilinx Answer 21453).
LogiCORE MAC v4.0
- Virtex-4 max number of cycles. See (Xilinx Answer 21511).
LogiCORE Pipelined Divider v3.0
- How to perform a Verilog Behavioral Simulation. See (Xilinx Answer 20615).
LogiCORE RAM-based Shift Register v8.0
- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).
3
KNOWN ISSUES in existing IPLogiCORE CIC v3.0
- The CIC v3.0 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).
LogiCORE CORDIC v3.0
- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).
LogiCORE DA FIR Filter, MAC FIR
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
LogiCORE DDC v1.0, MAC FIR v5.0
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).
LogiCORE DCT v2.1
- DCT can be implemented in the Spartan-3 and Virtex-4 devices. See (Xilinx Answer 18937).
LogiCORE DCT v2.1
- DCT output width is incorrectly calculated, causing Java errors. See (Xilinx Answer 20459).
LogiCORE DDS v5.0
- DDS Data Sheet has an obsolete web link. See (Xilinx Answer 21397).
LogiCORE DDS v5.0
- DDS channel output does not operate as expected. See (Xilinx Answer 21474).
LogiCORE 1024-pt FFTv1.0
- The block RAM configurations in the FFT/IFFT Data Sheet do not match the hardware configurations. See (Xilinx Answer 15311).
LogiCORE 16-pt FFT v2.0
- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).
LogiCORE 256-pt FFT v2.0
- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).
LogiCORE 32-pt FFT v1.0
- No Verilog model is available for the FFT Core. See (Xilinx Answer 11155).
LogiCORE 64-pt FFT v2.0
- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).
LogiCORE FFT
- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings. See (Xilinx Answer 14861).
- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).
LogiCORE MAC FIR v5.1
- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).
- Resetting Decimating MAC FIR does not cause RFD to assert. See (Xilinx Answer 20900).
LogiCORE Reed Solomon v5.0
- Information on the Ghost Enable pin in the GUI. See (Xilinx Answer 19526).
LogiCORE 3GPP Turbo Convolutional Decoder (TCC Decoder 3GPP) v1.0
- SDF constructs error in timing (post-PAR) simulation, when using ModelSim. See (Xilinx Answer 21434).