UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20778

LogiCORE Dual Port Block Memory - Register switch not turned on while generating BRAM

Description


Urgency: Standard 
 
General Description:  
While generating Dual Port Block Memory for Virtex-4 device (for 32-bit wide 4k depth with one pipeline stage), the DOA_REG/DOB_REG is activated but it does not turn on for 36-bit wide and 4k depth BRAM. Apparently, it does not activate for all width greater than 32. Why does this occur?

Solution


The issue is seen if "optimize for area" is selected which will generate the core using less RAMB as possible. When creating 4k deep by 36-bit wide, the COREGen uses 2k x 9 primitive (using a total of 8 RAMB16); 4 on the top row and 4 on the second row to get the total depth of 4k. Top and bottom rows are muxed and then registered using the registers in the fabric (not the RAMB16 reg). So, the outputs are properly registered. 
 
If you want to use the registers within the RAMB16, you should use "select Primitive" and choose 4k x 4 primitive, which will require 9 RAMB16 (not 8), but it will use the registers in the RAMB16. This should help with the performance if critical.
AR# 20778
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article