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AR# 20801

6.3 EDK Base System Builder (BSB) - PPC design with the processor debug signals brought to user I/O does not invert the halt signal

Description

When I bring the PowerPC debug signals to user I/O in a design created with Base System Builder (BSB), the PPC halt signal (DBGC405DEBUGHALT) is not being inverted correctly, preventing the use of some debugger cables. Why does this occur?

Solution

This problem occurs because the util_reduce_logic peripheral being used does not have an invert operation. However, you can invert the halt signal by using the util_vector_logic peripheral. 

 

For example, if BSB created: 

 

BEGIN util_reduce_logic 

PARAMETER INSTANCE = cpudbg_0_INV 

PARAMETER HW_VER = 1.00.a 

PARAMETER C_OPERATION = not 

PARAMETER C_SIZE = 1 

PORT Res = cpudbg_0_INV_Res_ppc405_0_DBGC405DEBUGHALT 

PORT Op1 = fpga_0_cpudbg_0_INV_Op1 

END 

 

change this to: 

 

BEGIN util_vector_logic 

PARAMETER INSTANCE = cpudbg_0_INV 

PARAMETER HW_VER = 1.00.a 

PARAMETER C_OPERATION = not 

PARAMETER C_SIZE = 1 

PORT Res = cpudbg_0_INV_Res_ppc405_0_DBGC405DEBUGHALT 

PORT Op1 = fpga_0_cpudbg_0_INV_Op1 

END 

 

This problem will be fixed in the 7.1 EDK software release.

AR# 20801
Date Created 09/03/2007
Last Updated 05/19/2014
Status Archive
Type General Article