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AR# 20805

11.1 EDK Base System Builder (BSB) - PowerPC JTAG signals brought to user I/O in a BSB-created design should be pulled up in the UCF

Description

When bringing the PowerPC JTAG signals to user I/O in a design created with Base System Builder, the PULLUP constraint is not placed on the JTAG signals in the UCF. Problems can result when there is no connection to the JTAG signals because they are left floating.

Solution

When you use the option in BSB to bring the CPU JTAG signals to user I/O, edit the UCF to add the PULLUP constraint to these signals.

For example, if a design created in BSB creates the user I/O ports:

PORT fpga_0_cpudbg_0_INV_Op1_pin = fpga_0_cpudbg_0_INV_Op1, DIR = INPUT, VEC = [0:0]

PORT fpga_0_ppc405_0_C405JTGTDO_pin = fpga_0_ppc405_0_C405JTGTDO, DIR = OUTPUT

PORT fpga_0_ppc405_0_JTGC405TDI_pin = fpga_0_ppc405_0_JTGC405TDI, DIR = INPUT

PORT fpga_0_ppc405_0_JTGC405TCK_pin = fpga_0_ppc405_0_JTGC405TCK, DIR = INPUT

PORT fpga_0_ppc405_0_JTGC405TMS_pin = fpga_0_ppc405_0_JTGC405TMS, DIR = INPUT

PORT fpga_0_ppc405_0_JTGC405TRSTNEG_pin = fpga_0_ppc405_0_JTGC405TRSTNEG, DIR = INPUT

add the following constraints in "sysmem.ucf" (found in the data directory):

Net fpga_0_cpudbg_0_INV_Op1_pin PULLUP;

Net fpga_0_ppc405_0_JTGC405TDI_pin PULLUP;

Net fpga_0_ppc405_0_JTGC405TCK_pin PULLUP;

Net fpga_0_ppc405_0_JTGC405TMS_pin PULLUP;

Net fpga_0_ppc405_0_JTGC405TRSTNEG_pin PULLUP;

AR# 20805
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article