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AR# 20819

7.1i EDK SP2-opb_spi_v1_00_c - In Master-mode, there are glitches on the SPI clock when data and clock change simultaneously

Description

General Description:

In Master-mode, the SPI Core drives data changing on the clock edge. This causes data alignment problems on the downstream SPI device.

Solution

This problem occurs if the local Slave Select on the Master (SPISEL) is left floating. To work around this, drive this line to a logic "1" in the MHS or top-level design by assigning the signal to "net_vcc."

AR# 20819
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article